Abstract: A variable resistive memory device includes a bit line, a word line, first electrodes and second electrodes, which are respectively arrayed in different directions, wherein a unit cell including a variable resistive material layer interposed between the first electrode and the second electrode is located at every intersection between the first electrode and the second electrode.

Abstract: The present invention discloses a nanoball solution coating method and applications thereof. The method comprises steps: using a scraper to coat a nanoball solution on a substrate to attach a plurality of nanoballs on the substrate; flushing or flowing through the substrate with a heated volatile solution to suspend the nanoballs unattached to the substrate in the volatile solution; and using the scraper to scrape off the volatile solution carrying the suspended nanoballs, whereby is simplified the process to coat nanoballs. The method can be used to fabricate nanoporous films, organic vertical transistors, and large-area elements and favors mass production.

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations.

Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

Abstract: The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.

Abstract: Low energy memristors with engineered switching channel materials include: a first electrode; a second electrode; and a switching layer positioned between the first electrode and the second electrode, wherein the switching layer includes a first phase comprising an insulating matrix in which is dispersed a second phase comprising an electrically conducting compound material for forming a switching channel.

Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

Abstract: A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.

Abstract: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode.

Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.

Abstract: Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.

Abstract: Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.

Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a dielectric structured as an operably variable resistance region between an oxygen source and an oxygen sink. The dielectric, oxygen source, and an oxygen sink can be structured as a field driven unipolar memory element with respect to generation and healing of a filament in the dielectric. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured. In some embodiments, the metal-rich host oxide is deposited using a modified atomic layer deposition (ALD) process. In other embodiments, the metal-rich host oxide is formed by depositing a metal-containing coupling layer on a host oxide and thermally processing both layers to create a metal-rich composite host oxide with a higher concentration of oxygen vacancies.

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: A protection circuit (FIG. 2) for an integrated circuit is disclosed. The protection circuit comprises a protection transistor (MN0) having a current path coupled between a first terminal (VDD) and a second terminal (GND). A current mirror (MP1, MP0, MN2, MN1) has an output terminal coupled to a control terminal of the protection transistor. A delay circuit (R1, C0) is connected between the first and second terminals and has a delay output terminal connected to a first input terminal (MN1) of the current mirror.

Abstract: A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.

Abstract: A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.

Abstract: Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.

Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract: A method of fabricating an integrated circuit is disclosed (FIGS. 1-2). The method comprises providing a substrate (200) having an isolation region (202) and etching a trench in the isolation region. A first conductive layer (214) is formed within the trench. A first transistor having a first conductivity type (n-channel) is formed at a face of the substrate. The first transistor has a gate (216) formed of the first conductive layer. A second transistor having a second conductivity type (p-channel) is formed at the face of the substrate. The second transistor has a gate (224) formed of the first conductive layer. The method further comprises replacing the first conductive layer of the first transistor with a first metal gate (132) and replacing the first conductive layer of the second transistor with a second metal gate (134).

Abstract: Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm).

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract: The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

Abstract: A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off.

Abstract: Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.

Abstract: A phase-change material, which has a high crystallization temperature and is superior in thermal stability of the amorphous phase, which has a composition of the general chemical formula GexMyTe100-x-y wherein M indicates one type of element which is selected from the group which comprises Al, Si, Cu, In, and Sn, x is 5.0 to 50.0 (at %) and y is 4.0 to 45.0 (at %) in range, and x and y are selected so that 40 (at %)?x+y?60 (at %). This phase-change material further contains, as an additional element L, at least one type of element L which is selected from the group which comprises N, O, Al, Si, P, Cu, In, and Sn in the form of GexMyLzTe100-x-y-z wherein z is selected so that 40 (at %)?x+y+z?60 (at %).

Abstract: A high density variable resistive random access memory device and a method of fabricating the same are provided. The device includes first word lines, each separated from each other by a width of first word line; bit lines, each separated from each other by a width of bit line; and second word lines, each located between two adjacent first word lines, wherein the widths of first word line and the bit line are substantially same, and the bit lines are located over the first and second word lines.

Abstract: A resistive memory device capable of suppressing disturbance between cells and a fabrication method thereof are provided. The resistive memory device includes a word line formed, in a first direction, on a semiconductor substrate, lower access structures, each having a pillar shape, formed on the word line, a first insulating layer formed around an outer circumference of each of the lower access structures, a heat-absorption layer formed on a surface of each of the to heat-absorption layers, a variable resistive material formed on the lower access structures, and an upper electrode formed on each variable resistive material.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: A resistance random access memory element includes a first electrode, an insulating layer, a diffusing metal layer, and a second electrode superimposed in sequence. The insulating layer includes a plurality of pointed electrodes. A method for making a resistance random access memory element includes growing and forming an insulating layer on a surface of a first electrode. A diffusing metal layer is formed on a surface of the insulating layer. A second electrode is mounted on a surface of the diffusing metal layer. A negative pole and a positive pole of a driving voltage are connected with the first and second electrodes, respectively. The diffusing metal in the diffusing metal layer is oxidized into metal ions by the driving voltage. The metal ions are driven into the insulating layer and form a plurality of pointed electrodes after reduction.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.

Abstract: An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array.

Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.