Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

Abstract: A forming method for a silicon-based display panel includes providing a silicon substrate having a display region and a peripheral region surrounding the display region, providing a first set of photomasks corresponding to the display region, using the first set of photo masks in an exposure process of the display region, providing a second set of photomasks corresponding to the peripheral region, and using the second set of photomasks in an exposure process of the peripheral region. The exposure process of the display region and the exposure process of the peripheral region are different process steps. According to the forming method for the silicon-based display panel, splicing of pixel patterns in the display region is not carried out, so that the yield and the display effect are improved.

Abstract: An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

Abstract: There is provided a technique that includes: forming an oxynitride film on at least one substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a precursor from a precursor supply part to the at least one substrate; (b) supplying an oxidizing agent from an oxidizing agent supply part to the at least one substrate; and (c) supplying a nitriding agent from a nitriding agent supply part to the at least one substrate, wherein in (b), an inert gas is supplied from an inert gas supply part, which is different from the oxidizing agent supply part, to the at least one substrate, and at least one of nitrogen concentration and refractive index of the oxynitride film formed on the at least one substrate is adjusted by controlling a flow rate of the inert gas.

Abstract: A method of fabricating a semiconductor device includes forming a back gate dielectric. A layer of two-dimensional material is transferred onto a surface of the back gate dielectric. A top gate dielectric is deposited and a top gate formed thereon. A first set of spacers is formed around the top gate and exposed portions of the top gate dielectric removed and a second set of spacers formed around the top gate. Exposed portions of the two-dimensional material are removed. A directional etch down of the substrate and a lateral isotropic etch of the substrate are performed and open spaces filled with a dielectric material surrounding the top gate, the back gate dielectric, and the substrate. The dielectric material is etched from the top gate and the back gate dielectric, the second set of spacers removed, and source and drain contact metal deposited. The source and drain contacts the layer.

Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

Abstract: The present invention relates to a method for manufacturing a cliché for offset printing and a cliché for offset printing.

Abstract: A pattern-forming method includes forming a base pattern having recessed portions on a front face side of a substrate directly or via other layer. The recessed portions of the base pattern are filled with a first composition to form a filler layer. Phase separation of the filler layer is allowed to form a plurality of phases of the filler layer. A part of the plurality of phases of the filler layer is removed to form a miniaturized pattern. The forming of the base pattern includes: forming a resist pattern on the front face side of the substrate; forming a layer of a second polymer on lateral faces of the resist pattern; and forming a layer of a third polymer that differs from the second polymer on a surface of the substrate or on a surface of the other layer.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.

Abstract: A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

Abstract: A method is disclosed involving depositing a neutral orientation template layer onto a substrate after formation of chemical epitaxy or graphoepitaxy features on the substrate, but before deposition and orientation of a self-assemblable polymer. The orientation layer is arranged to bond with the substrate but not with certain features, so that it may be easily removed by vacuum or rinsing with organic solvent. The neutral orientation layer has a chemical affinity to match that of blocks in the self-assemblable polymer so that blocks of differing types wet the neutral orientation layer so that domains in the self-assembled polymer may lie side by side along the substrate surface, with interfaces normal to the substrate surface. The resulting aligned and oriented self-assembled polymer may itself be used as a resist for device lithography of the substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate. The gate stack is formed over the first region. The method includes forming a negative photoresist layer over the first region and a first portion of the conductive layer over the isolation structure to cover the gate stack. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over a second portion of the conductive layer. The method includes removing the second portion through the trenches. The method includes removing the mask layer. The method includes removing the negative photoresist layer.

Abstract: The present invention relates to a TFT substrate manufacturing method. The TFT substrate manufacturing method includes: Step 10: applying a first mask-based operation to form a TFT gate electrode pattern on a base plate; Step 20: applying a second mask-based operation to form an active layer pattern and a source/drain metal electrode pattern on the base plate; Step 30: depositing a passivation layer on the base plate, applying a third mask-based operation to define a pixel electrode pattern, conducting etching and photoresist haze operations, and then depositing a pixel electrode; and Step 40: conducting etching or direct photoresist stripping to form the pixel electrode pattern.

Abstract: A method of manufacturing a structure including a substrate and a photosensitive resin layer provided on the substrate includes irradiating a region of the photosensitive resin layer with light in a state where a layer is provided on a surface of the substrate, the region being located above a space surrounded by the substrate and the photosensitive resin layer, and the surface facing the space, and removing a portion of the photosensitive resin layer located above the space to form a hole, wherein the provided layer has a reflectance of 40% or less with respect to the light.

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

Abstract: Methods for machining glass structures may be performed on fusion-drawn glass laminates having a core layer interposed between a first cladding layer and a second cladding layer. The core layer may be formed from a core glass composition having a core photosensitivity, the first cladding layer may be formed from a glass composition having a photosensitivity different from the core photosensitivity, and the second cladding layer may be formed from a glass composition having a photosensitivity different from the core photosensitivity. At least one of the core layer, the first cladding layer, and the second cladding layer is a photomachinable layer. The methods may include exposing a selected region of a photomachinable layer in the fusion-drawn laminate to ultraviolet radiation; heating the glass structure until the selected region crystallizes; and removing the crystallized material selectively from the photomachinable layer.

Abstract: Techniques herein include systems and methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers. Location-specific tuning of stress on semiconductor substrates reduces overlay error. Location-specific tuning of stress independently modifies specific regions, areas, or point locations on a substrate to change wafer bow at those specific locations, which reduces overlay error on substrates, which in turn improves overlay of subsequent patterns created on the substrate. Techniques herein include receiving a substrate with some amount of overlay error, measuring bow of the substrate to map z-height deviations across the substrate, generating an overlay correction pattern, and then physically modifying internal stresses on the substrate at specific locations with modifications independent of other coordinate locations. Such modifications can include etching a backside surface of the substrate. One or more processing modules can be used for such processing.

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Abstract: Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Abstract: Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

Abstract: The present disclosure relates to a fringe field switching type liquid crystal display. The present disclosure suggests a fringe field switching type liquid crystal display comprising: a substrate; a gate pad disposed on the substrate; a gate insulating layer covering the gate pad; a data pad disposed on the gate insulating layer; a first passivation layer covering the data pad; a common pad disposed on the first passivation layer; a protective metal layer disposed on the common pad; a second passivation layer covering the common pad; a gate contact hole exposing the gate pad; a data contact hole exposing the data pad; and a common contact hole exposing the protective metal layer.

Abstract: The present invention discloses an OGS touch screen, a manufacturing method thereof and an OGS touch device. The OGS touch screen includes a substrate; a first p-ITO array that is provided in a display area of the substrate, the first p-ITO array including a plurality of first p-ITO touch electrodes; and a second p-ITO array that is provided on the first p-ITO array, the second p-ITO array including a plurality of second p-ITO touch electrodes, wherein an interval between any two adjacent first p-ITO touch electrodes in the first p-ITO array is smaller than an interval between any two adjacent second p-ITO touch electrodes in the second p-ITO array.

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the first side of the circuit structure; an encapsulant formed on the first side of the circuit structure for encapsulating the electronic element; a dielectric layer formed on portions of the second side of the circuit structure; and a metal structure formed on the dielectric layer and the circuit structure. The metal structure has a first metal layer bonded to the circuit structure and a second metal layer formed on the first metal layer and the dielectric layer. Therefore, by replacing a conventional silicon interposer with the circuit structure, the invention eliminates the need to fabricate through silicon vias so as to greatly reduce the fabrication difficulty and cost. The invention further provides a method for fabricating the electronic package.

Abstract: An array substrate, a method of manufacturing the array substrate, and a display device are disclosed, for eliminating white Mura defects generated during the Cell process. The method comprises steps of: forming a display area and a non-display area on a substrate, a circuit bonding area being arranged within the non-display area; forming an alignment film within the display area through a patterning process; forming, through a patterning process, a transparent protection layer at least in a portion of the non-display area other than the circuit bonding area; and forming, through a rubbing-imprinting process, a plurality of lines having the same orientation on a surface of the alignment film, for an ordered arrangement of liquid crystal molecules, wherein a surface height of the transparent protection layer is lower than or equal to a surface height of the alignment film.

Abstract: A pattern formation method includes step (i) of forming a first negative type pattern on a substrate by performing step (i-1) of forming a first film on the substrate using an actinic ray-sensitive or radiation-sensitive resin composition, step (i-2) of exposing the first film and step (i-3) of developing the exposed first film in this order; step (iii) of forming a second film at least on the first negative type pattern using an actinic ray-sensitive or radiation-sensitive resin composition (2); step (v) of exposing the second film; and step (vi) of developing the exposed second film and forming a second negative type pattern at least on the first negative type pattern.

Abstract: An image sensor includes a pixel array chip, a logic chip, and an interposed layer. The interposed layer is disposed on the pixel array chip. The logic chip is disposed on the interposed layer. The interposed layer includes a connecting part, a shielding part, and a metal-diffusion barrier layer. The connecting part electrically connects a first interconnection wire of the pixel array chip and a second interconnection wire of the logic chip. The connecting part includes a first metallic element. The shielding part is disposed spatially apart from the connecting part and electrically grounded to suppress an electrical coupling between the pixel array chip and the logic chip. The shielding part includes a second metallic element. The metal-diffusion barrier layer is disposed on top and bottom surfaces of the interposed layer to limit diffusion of electrical charges to the pixel array chip and the logic chip.

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Abstract: A method of fabricating a wire grid polarizer includes sequentially forming a conductive layer, a guide layer, and a surface treatment protection layer on a substrate, patterning the surface treatment protection layer and the guide layer, forming a surface treatment film on side surfaces and upper surfaces of the first and second patterns, removing the first and second surface treatment protection patterns from the respective first and second patterns on which the surface treatment film is formed, to expose upper surfaces of the first and second guide patterns and providing a block copolymer of two monomers having mutually different etch rates into a space defined by the conductive layer and the first and second guide patterns, wherein a transfer layer which is hydrophobic to the block copolymer of two monomers is formed on the upper surfaces of the first and second guide patterns.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.

Abstract: A method includes depositing a first photoresist layer having a first thickness above a substrate, defining a first opening in the first photoresist layer by exposing the first photoresist layer to radiation, the first opening having a first width. The method includes depositing a conformal passivation layer directly on the first photoresist layer, and depositing a second photoresist layer having a second thickness on the conformal passivation layer. The method includes defining a second opening in the second photoresist layer by exposing the second photoresist layer to radiation, the second opening having a second width greater than the first width, and depositing a metal layer above the first photoresist layer and the substrate to form an electrode, a dielectric layer being provided to contact the metal layer. The method includes removing the first photoresist layer and the second photoresist layer. The first photoresist layer can include a positive photoresist.

Abstract: Provided are gap-fill methods.

Abstract: Molecular glass based planarizing compositions for lithographic processing are disclosed. The processes generally include casting the planarizing composition onto a surface comprised of lithographic features, the planarizing composition comprising at least one molecular glass and at least one solvent; and heating the planarizing composition to a temperature greater than a glass transition temperature of the at least one molecular glass. Exemplary molecular glasses include polyhedral oligomeric silsesquioxane derivatives, calixarenes, cyclodextrin derivatives, and other non-polymeric large molecules.

Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.

Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.

Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.

Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.

Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.

Abstract: A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween.