Epitaxial Deposition Of Group Iii-v Compound (epo) Patents (Class 257/E21.097)
E Subclasses
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Patent number: 8288186Abstract: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.Type: GrantFiled: September 22, 2010Date of Patent: October 16, 2012Assignee: Philips Lumileds Lighting Company LLCInventors: Michael R. Krames, Nathan F. Gardner, John E. Epler
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Patent number: 8283239Abstract: High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 106 cm?2.Type: GrantFiled: December 15, 2006Date of Patent: October 9, 2012Assignee: Saint-Gobain Cristaux & DetecteursInventors: Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart, Therese Gibart, legal representative
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Patent number: 8273592Abstract: The object of the present invention is to provide a method of manufacturing a Group-III nitride semiconductor light-emitting device that is highly productive and that enables production of a device having excellent light-emitting properties; a Group-III nitride semiconductor light-emitting device; and a lamp using the light emitting device.Type: GrantFiled: December 5, 2007Date of Patent: September 25, 2012Assignee: Showa Denko K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
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Patent number: 8236593Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.Type: GrantFiled: May 14, 2008Date of Patent: August 7, 2012Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State UniversityInventors: Chantal Arena, Subhash Mahajan, Ilsu Han
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Patent number: 8227327Abstract: There is provided a method for epitaxial growth, wherein a quantum dot is formed on an epitaxial layer using a quantum-dot forming material with an excellent lattice matching property, and the formed quantum dot is positioned on a defect in the epitaxial layer, thereby minimizing transfer of the defect into an epitaxial layer formed through a subsequent process. The method includes preparing a first epitaxial layer having a defect formed therein; coating an anti-surfactant on the first epitaxial layer; supplying a quantum-dot forming material lattice-matched with respect to the first epitaxial layer, thereby forming a quantum dot obtained by allowing the anti-surfactant to react with the quantum-dot forming material on the first epitaxial layer; allowing the quantum dot to be moved onto a step of the first epitaxial layer due to a difference of surface energies between the quantum dot and the first epitaxial layer; and growing a second epitaxial layer on the first epitaxial layer.Type: GrantFiled: February 18, 2009Date of Patent: July 24, 2012Assignee: Industry-University Cooperation Foundation Hanyang UniversityInventor: Jae-eung Oh
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Publication number: 20120168877Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Inventors: Niloy Mukherjee, Gilbert Dewey, Marko Radosavljevic, Robert S. Chau, Matthew V. Metz
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Patent number: 8212288Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.Type: GrantFiled: September 10, 2010Date of Patent: July 3, 2012Assignee: Covalent Materials CorporationInventors: Jun Komiyama, Kenichi Eriguchi, Hiroshi Oishi, Yoshihisa Abe, Akira Yoshida, Shunichi Suzuki
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Patent number: 8202793Abstract: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.Type: GrantFiled: August 12, 2010Date of Patent: June 19, 2012Assignee: Kyma Technologies, Inc.Inventors: Edward A. Preble, Denis Tsvetkov, Andrew D. Hanser, N. Mark Williams, Xueping Xu
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Patent number: 8193016Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.Type: GrantFiled: January 6, 2011Date of Patent: June 5, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
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Patent number: 8188573Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.Type: GrantFiled: September 14, 2009Date of Patent: May 29, 2012Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Suh-Fang Lin, Wei-Hung Kuo
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Patent number: 8178427Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.Type: GrantFiled: March 10, 2010Date of Patent: May 15, 2012Assignees: Commissariat a. l'Energie Atomique, S.O.I. Tec Silicon on Insulator Technologies, S.A.Inventors: Chantal Arena, Laurent Clavelier, Marc Rabarot
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Patent number: 8173469Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.Type: GrantFiled: March 17, 2011Date of Patent: May 8, 2012Assignee: LG Innotek Co., Ltd.Inventors: Kyung Wook Park, Myung Hoon Jung
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Patent number: 8154050Abstract: A semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions includes an element formation region formed in the major surface of a semiconductor substrate, a gate electrode formed on a part of the element formation region, the semiconductor epitaxial layers formed in the source/drain regions of the element formation region so as to sandwich the channel region below the gate electrode, and silicide layers formed on the gate electrode and semiconductor epitaxial layers. Each semiconductor epitaxial layer has a three-layered structure in which first semiconductor films different in material or composition from the semiconductor substrate sandwich a second semiconductor film having a silicidation reactivity higher than that of the first semiconductor films. Each silicide layer extends to the second semiconductor film along the interface between the semiconductor substrate and semiconductor epitaxial layer.Type: GrantFiled: August 7, 2008Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Gaku Sudo
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Patent number: 8148241Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.Type: GrantFiled: July 23, 2010Date of Patent: April 3, 2012Assignee: Applied Materials, Inc.Inventors: Jie Su, Olga Kryliouk
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Patent number: 8148252Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: March 2, 2011Date of Patent: April 3, 2012Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 8143615Abstract: A superlattice structure comprises a plurality of well layers made of first semiconductor and a plurality of barrier layers made of second semiconductor that has a band gap wider than that of the first semiconductor, wherein both layers are deposited alternately, and wherein a maximum thickness of each of the wall and barrier layers is such that a band gap between a lower limit of a mini band generated in a conduction band and an upper limit of a mini band generated in a valence band is a given width in the energy state of electron of the superlattice structure, and a minimum thickness of each of the wall and the barrier layers is such that a bandwidth of a mini band generated in the conduction band is a given width in the energy state of electron of the superlattice structure.Type: GrantFiled: October 27, 2009Date of Patent: March 27, 2012Assignee: RikenInventor: Tomohiro Nishitani
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Patent number: 8143646Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.Type: GrantFiled: August 2, 2006Date of Patent: March 27, 2012Assignee: Intel CorporationInventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
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Patent number: 8133806Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: GrantFiled: September 30, 2010Date of Patent: March 13, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Christiaan J. Werkhoven
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Patent number: 8110889Abstract: In one embodiment a method for fabricating a compound nitride semiconductor device comprising positioning one or more substrates on a susceptor in a processing region of a metal organic chemical vapor deposition (MOCVD) chamber comprising a showerhead, depositing a gallium nitride layer over the substrate with a thermal chemical-vapor-deposition process within the MOCVD chamber by flowing a first gallium containing precursor and a first nitrogen containing precursor through the showerhead into the MOCVD chamber, removing the one or more substrates from the MOCVD chamber without exposing the one or more substrates to atmosphere, flowing a chlorine gas into the processing chamber to remove contaminants from the showerhead, transferring the one or more substrates into the MOCVD chamber after removing contaminants from the showerhead, and depositing an InGaN layer over the GaN layer with a thermal chemical-vapor-deposition process within the MOCVD chamber is provided.Type: GrantFiled: March 24, 2010Date of Patent: February 7, 2012Assignee: Applied Materials, Inc.Inventor: Olga Kryliouk
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Patent number: 8039371Abstract: A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor -on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on -insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.Type: GrantFiled: July 1, 2009Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana
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Patent number: 8039369Abstract: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 ?m. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs quantum dots formed on the first GaAs layer, a third InGaAs layer formed on the second InAs thin film layer having the plurality of InAs quantum dots, and a fourth GaAs layer formed on the third InGaAs layer, wherein the As source is As2.Type: GrantFiled: August 27, 2008Date of Patent: October 18, 2011Assignee: National Institute of Advanced Industrial Science and TechnologyInventor: Takeru Amano
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Patent number: 8030101Abstract: A method of manufacturing a low defect density GaN material comprising at least two steps of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially competent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence.Type: GrantFiled: May 18, 2009Date of Patent: October 4, 2011Assignee: Saint-Gobain Cristaux et DetecteursInventors: Eric Frayssinet, Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart
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Patent number: 8030679Abstract: Disclosed is a nitride semiconductor light emitting device including: one or more AllnN layers; an In-doped nitride semiconductor layer formed above the AllN layers; a first electrode contact layer formed above the In-doped nitride semiconductor layer; an active layer formed above the first electrode contact layer; and a p-type nitride semiconductor layer formed above the active layer. According to the nitride semiconductor light emitting device, a crystal defect of the active layer is suppressed, so that the reliability of the nitride semiconductor light emitting device is increased and the light output is enhanced.Type: GrantFiled: October 6, 2005Date of Patent: October 4, 2011Assignee: LG Innotek Co., Ltd.Inventors: Hyo Kun Son, Suk Hun Lee
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Patent number: 8022412Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.Type: GrantFiled: January 15, 2010Date of Patent: September 20, 2011Assignee: National Chung-Hsien UniversityInventors: Dong-Sing Wuu, Ray-Hua Horng, Shih-Ting Chen, Tshung-Han Tsai, Hsueh-Wei Wu
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Patent number: 7989244Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.Type: GrantFiled: May 23, 2007Date of Patent: August 2, 2011Assignee: Samsung LED Co., Ltd.Inventors: Kyoung-kook Kim, Kwang-ki Choi, June-o Song, Suk-ho Yoon, Kwang-hyeon Baik, Hyun-soo Kim
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Patent number: 7989926Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.Type: GrantFiled: September 12, 2006Date of Patent: August 2, 2011Assignee: Showa Denko K.K.Inventor: Takashi Udagawa
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Patent number: 7989238Abstract: Provided is a Group III nitride-based compound semiconductor light-emitting device including aluminum regions. The Group III nitride-based compound semiconductor light-emitting device includes a sapphire substrate; aluminum regions which are formed on the substrate; an AlN buffer layer; an Si-doped GaN n-contact layer; an n-cladding layer formed of multiple layer units, each including an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer; an MQW light-emitting layer including alternately stacked eight well layers formed of In0.2Ga0.8N and eight barrier layers formed of GaN and Al0.06Ga0.94N; a p-cladding layer formed of multiple layers including a p-type Al0.3Ga0.7N layer and a p-type In0.08Ga0.92N layer; a p-contact layer having a layered structure including two p-type GaN layers having different magnesium concentrations; and an ITO light-transmitting electrode.Type: GrantFiled: June 10, 2009Date of Patent: August 2, 2011Assignee: Toyoda Gosei Co., Ltd.Inventor: Koji Okuno
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Patent number: 7977706Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.Type: GrantFiled: August 13, 2010Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Anthony J. Lochtefeld
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Patent number: 7977134Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.Type: GrantFiled: October 6, 2006Date of Patent: July 12, 2011Assignee: Samsung LED Co., Ltd.Inventors: Hyuk Min Lee, Hyun Kyung Kim, Dong Joon Kim, Hyoun Soo Shin
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Patent number: 7964479Abstract: The present invention provides a method for forming a layer (6) of polycrystalline semiconductor material on a substrate (1). The method comprises providing at least one catalyst particle (4) on a substrate (1), the at least one catalyst particle (4) comprising at least a catalyst material, the catalyst material having a melt temperature of between room temperature and 500° C., or being able to form a catalyst material/semiconductor material alloy with a eutectic temperature of between room temperature and 500° C., and forming a layer (6) of polycrystalline semiconductor material on the substrate (1) at temperatures lower than 500° C. by using plasma enhancement of a precursor gas, thereby using the at least one catalyst particle (4) as an initiator. The present invention furthermore provides a layer (6) of polycrystalline semiconductor material obtained by the method according to embodiments of the present invention.Type: GrantFiled: February 19, 2008Date of Patent: June 21, 2011Assignee: IMECInventors: Francesca Iacopi, Philippe M. Vereecken
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Patent number: 7964424Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.Type: GrantFiled: November 5, 2008Date of Patent: June 21, 2011Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Patent number: 7960292Abstract: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices.Type: GrantFiled: May 2, 2009Date of Patent: June 14, 2011Assignee: Atomic Energy Council-Institute of Nuclear Energy ResearchInventor: Tsun-Neng Yang
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Patent number: 7951693Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.Type: GrantFiled: December 22, 2006Date of Patent: May 31, 2011Assignee: Philips Lumileds Lighting Company, LLCInventors: Patrick N. Grillot, Nathan F. Gardner, Werner K. Goetz, Linda T. Romano
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Patent number: 7943407Abstract: A method for manufacturing a semiconductor laser includes the steps of forming a mask layer having a stripe-shaped mask portion corresponding to a ridge stripe to be formed on a nitride-based group III-V compound semiconductor layer, etching the nitride-based group III-V compound semiconductor layer to a predetermined depth using the mask layer to form the ridge stripe, forming a resist to cover the mask layer and the nitride-based group III-V compound semiconductor layer, etching-back the resist until the stripe-shaped mask portion of the mask layer is exposed, removing the exposed mask portion of the mask layer by etching to expose the upper surface of the ridge stripe, forming a metal film on the resist and the exposed ridge stripe to form an electrode on the ridge stripe, removing the resist together with the metal film formed thereon, and removing the mask layer by etching.Type: GrantFiled: November 16, 2009Date of Patent: May 17, 2011Assignee: Sony CorporationInventors: Tsuyoshi Fujimoto, Nozomi Ohashi, Masaru Kuramoto, Eiji Nakayama
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Patent number: 7935615Abstract: A self-supported III-V nitride semiconductor substrate having a substantially uniform carrier concentration distribution in a surface layer existing from a top surface to a depth of at least 10 ?m is produced by growing a III-V nitride semiconductor crystal while forming a plurality of projections on a crystal growth interface at the initial or intermediate stage of crystal growth; conducting the crystal growth until recesses between the projections are buried, so that the crystal growth interface becomes flat; and continuing the crystal growth to a thickness of 10 ?m or more while keeping the crystal growth interface flat.Type: GrantFiled: September 18, 2007Date of Patent: May 3, 2011Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
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Patent number: 7915150Abstract: A method of manufacturing a nitride semiconductor substrate according to example embodiments may include forming a buffer layer on a (100) plane of a silicon (Si) substrate. The buffer layer may have a hexagonal crystal system and a (1010) plane. A nitride semiconductor layer may be epitaxially grown on the buffer layer. The nitride semiconductor layer may have a (1010) plane. Accordingly, because example embodiments enable the use of a relatively inexpensive Si substrate, a more economical nitride semiconductor substrate having a relatively large diameter may be achieved.Type: GrantFiled: July 10, 2008Date of Patent: March 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-soo Park, Dae-ho Yoon
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Patent number: 7901966Abstract: A method for manufacturing a nitride semiconductor device, comprises: epitaxially growing a semiconductor layer of a GaN-based material on the Ga surface of a GaN substrate while the GaN substrate is mounted on a substrate holder the substrate warping during the epitaxial growth so that a epitaxial deposit is deposited on the N surface of the substrate; and subjecting the N surface of the GaN substrate to vacuum suction after the epitaxial growth of the semiconductor layer; removing the epitaxial deposit from the N side of the GaN substrate after the semiconductor layer has been epitaxially grown, and before the N surface of the n-type GaN substrate is subjected to vacuum suction.Type: GrantFiled: August 4, 2009Date of Patent: March 8, 2011Assignee: Mitsubishi Electric CorporationInventors: Shinji Abe, Kazushige Kawasaki
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Patent number: 7897490Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.Type: GrantFiled: November 30, 2006Date of Patent: March 1, 2011Assignee: Kyma Technologies, Inc.Inventors: Edward A. Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
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Patent number: 7867799Abstract: A method of fabricating a continuous wave semiconductor laser diode in the (Al,Ga,In)N materials system comprises: growing, in sequence, a first cladding region (4), a first optical guiding region (5), an active region (6), a second optical guiding region (7) and a second cladding region (8). Each of the first cladding region (4), the first optical guiding region (5), the active region (6), the second optical guiding region (7) and the second cladding region (8) is deposited by molecular beam epitaxy.Type: GrantFiled: October 27, 2004Date of Patent: January 11, 2011Assignee: Sharp Kabushiki KaishaInventors: Stewart Hooper, Valerie Bousquet, Katherine L. Johnson, Matthias Kauer, Jonathan Heffernan
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Patent number: 7863167Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.Type: GrantFiled: February 13, 2009Date of Patent: January 4, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata
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Publication number: 20100314662Abstract: A semiconductor structure is formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase on a (0001) oriented semiconductor substrate. The structure comprises a bottom cladding layer, a top cladding layer, and a diffusion region positioned between the cladding layers for diffusing light propagating within the semiconductor structure. The diffuse region has refractive index different from those of the cladding layers and non-flat surfaces for providing light diffusing interfaces between the diffusion region and the cladding layers. According to the invention, the diffusion region comprises a plurality of diffusion layers, compositions and thicknesses of said diffusion layers having been chosen to avoid formation of strain-induced dislocations in the diffusion region, and adjacent diffusion layers having different refractive indices in order to further enhance the diffusion efficiency.Type: ApplicationFiled: July 2, 2010Publication date: December 16, 2010Inventors: Vladislav E. Bougrov, Maxim A. Odnoblyudov
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Patent number: 7842588Abstract: A method for forming a group-III metal nitride material film attached to a substrate including subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and heating the substrate to a temperature of between approximately 500° C.-800° C. The method further includes introducing a group III metal vapor to the surface of the substrate at a base pressure of at least 0.01 Pa, until a plurality of group III metal drops form on the surface, and introducing active nitrogen to the surface at a working pressure of between 0.05 Pa and 2.5 Pa, until group III metal nitride molecules form on the group III metal drops.Type: GrantFiled: February 21, 2008Date of Patent: November 30, 2010Assignee: Mosaic CrystalsInventor: Moshe Einav
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Patent number: 7838903Abstract: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.Type: GrantFiled: November 5, 2009Date of Patent: November 23, 2010Assignee: Fujitsu LimitedInventors: Toshihide Kikkawa, Kenji Imanishi
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Publication number: 20100285657Abstract: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently.Type: ApplicationFiled: May 5, 2010Publication date: November 11, 2010Applicant: SIXPOINT MATERIALS, INC.Inventors: Tadao HASHIMOTO, Edward Letts
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Publication number: 20100279461Abstract: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices.Type: ApplicationFiled: May 2, 2009Publication date: November 4, 2010Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCHInventor: Tsun-Neng YANG
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Publication number: 20100279495Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.Type: ApplicationFiled: April 30, 2010Publication date: November 4, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masaki UENO, Yusuke YOSHIZUMI, Takao NAKAMURA
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Patent number: 7824942Abstract: A method of fabricating a photoelectric device of Group III nitride semiconductor comprises the steps of: forming a first Group III nitride semiconductor layer on a surface of an original substrate; forming a patterned epitaxial-blocking layer on the first Group III nitride semiconductor layer; forming a second Group III nitride semiconductor layer on the epitaxial-blocking layer and the first Group III nitride semiconductor layer not covered by the epitaxial-blocking layer and then removing the epitaxial-blocking layer; forming a third Group III nitride semiconductor layer on the second Group III nitride semiconductor layer; depositing or adhering a conductive layer on the third Group III nitride semiconductor layer; and releasing a combination of the third Group III nitride semiconductor layer and the conductive layer apart from the second Group III nitride semiconductor layer.Type: GrantFiled: April 17, 2009Date of Patent: November 2, 2010Assignees: Zhanjing Technology (Shen Zhen) Inc., Advanced Optoelectronic Technology, Inc.Inventors: Po Min Tu, Shih Cheng Huang, Wen Yu Lin, Chih Peng Hsu, Shih Hsiung Chan
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Patent number: 7816238Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.Type: GrantFiled: June 11, 2008Date of Patent: October 19, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Osada, Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Takashi Kyono, Katsushi Akita, Yoshiki Miura
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Publication number: 20100244040Abstract: A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer (12) made of a group-III nitride compound on a substrate (11) by activating and reacting gas including a group-V element with a metal material in plasma; and sequentially forming an n-type semiconductor layer (14), a light-emitting layer (15), and a p-type semiconductor layer (16) each made of a group-III nitride compound semiconductor on the intermediate layer (12). Nitrogen is used as the group-V element, and the thickness of the intermediate layer (12) is in the range of 20 to 80 nm.Type: ApplicationFiled: November 5, 2007Publication date: September 30, 2010Applicant: SHOWA DENKO K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
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Patent number: 7803717Abstract: Epitaxial gallium nitride is grown on a silicon substrate while reducing or suppressing the formation of a buffer layer. The gallium nitride may be grown directly on the silicon substrate, for example using domain epitaxy. Alternatively, less than one complete monolayer of silicon nitride may be formed between the silicon and the gallium nitride. Subsequent to formation of the gallium nitride, an interfacial layer of silicon nitride may be formed between the silicon and the gallium nitride.Type: GrantFiled: October 21, 2004Date of Patent: September 28, 2010Assignee: North Carolina State UniversityInventors: Thomas A. Rawdanowicz, Jagdish Narayan