Deposition On A Semiconductor Substrate Which Is Different From The Semiconductor Material Being Deposited, I.e., Formation Of Heterojunctions (epo) Patents (Class 257/E21.103)
  • Patent number: 10276725
    Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 10109711
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Anand S Murthy, Glenn A Glass, Kelin J Kuhn, Tahir Ghani
  • Patent number: 9818884
    Abstract: An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady, Harold W. Kennel
  • Patent number: 9490118
    Abstract: A method for manufacturing a germanium (Ge) epitaxial layer is provided. First, a substrate is provided. Then, a first deposition process is performed to deposit a first Ge epitaxial film on the substrate. Next, a first annealing process is performed on the first Ge epitaxial film. Following that, a second deposition process is performed to directly deposit a second Ge epitaxial film on the first Ge epitaxial film. Thereafter, a second annealing process is performed on the second Ge epitaxial film, wherein the Ge epitaxial layer includes the first Ge epitaxial film and the second Ge epitaxial film, and a thickness of the Ge epitaxial layer is greater than 0.5 microns.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jaw-Jyh Tseng, Chun-Ming Chen, Yao-Yi Huang
  • Patent number: 9437496
    Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei, Werner A. Rausch
  • Patent number: 8906758
    Abstract: The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: December 9, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Miguel E. Urteaga
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 8815712
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8815684
    Abstract: A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Robert H. Dennard, Bruce B. Doris, Barry P. Linder, Ramachandran Muralidhar, Ghavam G. Shahidi
  • Patent number: 8722520
    Abstract: A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mark van Dal
  • Publication number: 20130233240
    Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: ASM AMERICA, INC.
    Inventors: Nyles W. Cody, Shawn G. Thomas
  • Publication number: 20130040438
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Publication number: 20130032857
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Application
    Filed: July 6, 2012
    Publication date: February 7, 2013
    Applicant: The Arizona Board of Regents, a body corporate acting on behalf of Arizona State University
    Inventors: John Kouvetakis, Cole J. Ritter, III, Changwu Hu, Ignatius S.T. Tsong, Andrew Chizmeshya
  • Patent number: 8361867
    Abstract: A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. Trenches are etched through a pre-metal dielectric to the contacts of the FET. Etching extends further into the substrate, through the surface silicon layer, through the silicon germanium layer and into the substrate below the silicon germanium layer. The further etch is performed to a depth to allow for sufficient edge relaxation to induce a desired level of longitudinal strain to the surface layer of the FET. Subsequent processing forms contacts extending through the pre-metal dielectric and at least partially into the trenches within the substrate.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: January 29, 2013
    Assignee: Acorn Technologies, Inc.
    Inventor: Paul A. Clifton
  • Patent number: 8247261
    Abstract: A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra Sadana
  • Publication number: 20120138897
    Abstract: Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hsiang Lin, Jeff J. Xu, Pang-Yen Tsai
  • Publication number: 20110306189
    Abstract: A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 15, 2011
    Inventors: Xiaohua Cheng, Shengan Xiao
  • Patent number: 8076223
    Abstract: The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T1 that is higher than 800° C., the removal of the natural oxide film from the surface of the SiGe constant composition layer is performed in a reducing atmosphere through a heat treatment at a temperature T2 that is equal to or higher than 800° C.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: December 13, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Patent number: 8062963
    Abstract: A method is described which includes providing a semiconductor substrate and forming a trench in the semiconductor substrate. An epitaxy region is grown in the trench. An amorphous layer is deposited overlying the epitaxy region. The semiconductor substrate is then annealed. The anneal may convert a portion of the amorphous layer to crystalline material, as found in the epitaxy region. A chemical mechanical polish (CMP) is then performed, which may remove a portion of the amorphous layer which has not been converted. In an embodiment, the amorphous layer and epitaxy region are germanium and the semiconductor substrate is silicon. The formed crystalline region may be used to form a channel of a p-type device.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mark van Dal
  • Patent number: 8026535
    Abstract: In a thin film transistor, a semiconductor layer containing Si and Ge is applied, a Ge concentration of this semiconductor layer is high at the side of the insulating substrate, and crystalline orientation of the semiconductor layer indicates a random orientation in a region of 20 nm from the side of the insulating substrate, and indicates a (111), (110) or (100) preferential orientation at the film surface side of the semiconductor layer.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 27, 2011
    Assignees: Hitachi, Ltd., Tokyo Institute of Technology
    Inventors: Masatoshi Wakagi, Junichi Hanna
  • Patent number: 7989295
    Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 2, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7977221
    Abstract: A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: July 12, 2011
    Assignees: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
  • Patent number: 7935617
    Abstract: A method of providing a layer in a semiconductor device, wherein the layer includes Si1-x-yGexCy, and wherein the carbon in the layer is in a stable condition, includes preparing a silicon substrate; preparing a SiGeC precursor; forming a Si1-x-yGexCy layer on the silicon substrate from the precursor; forming a top silicon layer on the Si1-x-yGexCy layer; and completing the semiconductor device.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 3, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Douglas J. Tweet
  • Patent number: 7902025
    Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: March 8, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7897495
    Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Andrew M. Lam, Yihwan Kim
  • Patent number: 7863163
    Abstract: A method for depositing a carbon doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 700 torr in a process chamber housing a patterned substrate having exposed single crystal material. The method further comprises providing a flow of a silicon source gas to the process chamber. The silicon source gas comprises dichlorosilane. The method further comprises providing a flow of a carbon precursor to the process chamber. The method further comprises selectively depositing the carbon doped epitaxial semiconductor layer on the exposed single crystal material.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 4, 2011
    Assignee: ASM America, Inc.
    Inventor: Matthias Bauer
  • Patent number: 7851379
    Abstract: There are provided a substrate processing method and apparatus adapted to prevent deterioration of film thickness uniformity while maintaining the film forming rate. The substrate processing method comprises: (a) accommodating a plurality of substrates in a process chamber by carrying and stacking the substrates in the process chamber, (b) forming first amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying first gas, and (c) forming second amorphous silicon films to a predetermined thickness by heating at least the substrates and supplying second gas different from the first gas. The first gas is higher order gas than the second gas.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: December 14, 2010
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii
  • Patent number: 7812396
    Abstract: A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh
  • Patent number: 7800116
    Abstract: A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Murata, Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7785995
    Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: August 31, 2010
    Assignees: ASM America, Inc., S.O.I. Tec Silicon on Insulator Technologies, S.A.
    Inventors: Nyles W. Cody, Chantal Arena, Pierre Tomasini, Carlos Mazure
  • Patent number: 7786488
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 31, 2010
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 7772127
    Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: August 10, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Christophe Figuet, Mark Kennard
  • Patent number: 7767560
    Abstract: The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Robert S. Chau, Brian S. Doyle, Jack T. Kavalieros
  • Patent number: 7723214
    Abstract: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: May 25, 2010
    Assignee: Siltronic AG
    Inventor: Peter Storck
  • Patent number: 7718469
    Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: May 18, 2010
    Inventor: Mohamed-Ali Hasan
  • Patent number: 7678645
    Abstract: Method for forming a highly relaxed epitaxial semiconductor layer (52) with a thickness between 100 nm and 800 nm in a growth chamber includes four principle steps. In a first step, the method provides a substrate (51) in the growth chamber on a substrate carrier. In a second step, the method maintains a constant substrate temperature (TS) of the substrate (51) in a range between 350° C. and 500° C. In a third step, the method establishes a high-density, low-energy plasma in the growth chamber such that the substrate (51) is being exposed to the plasma. In a fourth step, the method directs Silane gas (SiH4) and Germane gas (GeH4) through the gas inlet into the growth chamber, the flow rates of the Silane gas and the Germane gas being adjusted in order to form said semiconductor layer (52) by means of vapor deposition with a growth rate in a range between 1 and 10 nm/s. The semiconductor layer (52) has a Germanium concentration x in a range between 0<x<50%.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: March 16, 2010
    Assignee: Eidgenoessische Technische Hochschule Zuerich
    Inventor: Hans Von Kaenel
  • Patent number: 7671383
    Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: March 2, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20090294801
    Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 3, 2009
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.
    Inventors: Eric C. T. Harley, Judson R. Holt, Dominic J. Schepis, Michael D. Steigerwalt, Linda Black, Rick Carter
  • Patent number: 7575973
    Abstract: A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: August 18, 2009
    Assignee: SanDisk 3D LLC
    Inventors: Nima Mokhlesi, Roy Scheuerlein
  • Publication number: 20090090933
    Abstract: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 9, 2009
    Applicants: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
  • Publication number: 20090085027
    Abstract: The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: September 29, 2007
    Publication date: April 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Been-Yih Jin, Robert S. Chau, Brian S. Doyle, Jack T. Kavalieros
  • Publication number: 20090072271
    Abstract: Disclosed is a method of growing thin and smooth germanium (Ge) on a strained or relaxed silicon (Si) layer comprising the steps of: (a) treating surface of the strained or relaxed Si layer to gaseous precursors of both Si (e.g., silane) and Ge (e.g., germane) for a predetermined short time duration ?t, where 1??t?30 seconds; and (b) depositing a thin Ge film on top of said treated Si layer, wherein said treatment step of (a) reduces growth time and surface roughness of the thin Ge film (e.g., sub-5 nm or sub-20 nm thick) deposited on the Si layer. The treatment step (a) can be conducted at a steady predetermined temperature T, where 450?T?900° C. The predetermined short time duration ?t can be chosen such that less than 10 A of SiGe is deposited.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 19, 2009
    Inventors: Leonardo Gomez, Meekyung Kim, Judy L. Hoyt
  • Publication number: 20090061604
    Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 5, 2009
    Applicants: CANON KABUSHIKI KAISHA, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
  • Patent number: 7498630
    Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ichige, Koji Hashimoto, Tatsuaki Kuji, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Koji Sakui
  • Publication number: 20090045412
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Application
    Filed: May 23, 2006
    Publication date: February 19, 2009
    Inventor: Takashi Udagawa
  • Patent number: 7439567
    Abstract: An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the Y-direction portions to define two non-volatile memory transistors in each memory cell. Memory cells are replicated in the word line direction and then mirrored with respect to the word line to form the next row or column. This geometry is contactless because the word line and source/drain regions are all linear throughout the array so that electrical contact can be established outside of the array of cells. Each transistor can be addressed and thus programmed and erased or pairs of transistors in a line can be erased, i.e.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: October 21, 2008
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7429766
    Abstract: In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Publication number: 20080194078
    Abstract: To obtain a semiconductor substrate having a high-quality Ge-based epitaxial film in a large area, a SiGe mixed crystal buffer layer and a Ge epitaxial film is grown on a main surface of a Si substrate 10. Although high-density defects are introduced in the Ge epitaxial film 11 from an interface between the Ge epitaxial film 11 and the Si substrate 10, the Ge epitaxial film is subjected to a heat treatment at a temperature of not less than 700° C. and not more than 900° C. to cause threading dislocations 12 to change into dislocation-loop defects 12? near the interface between the Ge epitaxial film 11 and the Si substrate.
    Type: Application
    Filed: January 29, 2008
    Publication date: August 14, 2008
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Publication number: 20080169468
    Abstract: Provided is a method and apparatus for fabricating a polycrystalline silicon film using a transparent substrate. The method includes forming a light absorption layer on a surface of the transparent substrate; and heating the light absorption layer using irradiation of Rapid Thermal Process (RTP) light source, while depositing the polycrystalline silicon film on the light absorption layer.
    Type: Application
    Filed: November 14, 2006
    Publication date: July 17, 2008
    Applicant: POINT ENGINEERING CO., LTD
    Inventor: Bum Mo Ahn
  • Patent number: 7399686
    Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers. The method further includes forming a nitride cap layer on the second semiconductor layer prior to forming the third semiconductor layer. Semiconductor structure formed by the above method is also described.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Howard Hao Chen, Louis Lu-Chen Hsu, Jack Allan Mandelman