Using Reduction Or Decomposition Of Gaseous Compound Yielding Solid Condensate, I.e., Chemical Deposition (epo) Patents (Class 257/E21.101)
  • Patent number: 10593558
    Abstract: A method of manufacturing a solar cell is disclosed. The method of manufacturing the solar cell includes depositing an intrinsic amorphous silicon layer on a surface of a semiconductor substrate, depositing an amorphous silicon layer containing impurities on the intrinsic amorphous silicon layer to form a conductive region, and forming an electrode electrically connected to the conductive region. The depositing of the intrinsic amorphous silicon layer includes depositing the intrinsic amorphous silicon on the surface of the semiconductor substrate at a deposition rate of 0.5 nm/sec to 2.0 nm/sec.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 17, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyoungsoo Lee, Sunghyun Hwang, Sangwook Park
  • Patent number: 10563305
    Abstract: Described herein are systems and methods using same for the storage and delivery of chemical precursors that are used in the manufacture of a semiconductor device. In one aspect, the storage system comprises the chemical precursors and a container and the systems have an inlet jet design. The chemical precursor has a low vapor pressure less than about 50 Torr-absolute at container temperature set for delivery. The delivery system further contains a carrier gas. The inlet jet design can deliver the carrier gas at a certain pressure and a certain low rate to impinge upon the surface of the chemical precursors to produce a vapor or droplets of the chemical precursor. The vapor or droplets of the chemical precursor then combine with the carrier gas to provide a precursor-laden fluid stream which will be passed to and used in the processing tool.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 18, 2020
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: James Patrick Nehlsen, Charles Michael Birtcher
  • Patent number: 10460922
    Abstract: The present disclosure generally relates to methods and apparatus for heating a substrate as well as a slot management method for a thermal treatment chamber that in one embodiment includes providing a first substrate to a first slot of a carrier in the thermal treatment chamber via a transfer opening formed in the thermal treatment chamber, the first substrate having a specified anneal time, heating the substrate, moving the carrier to a lowermost position in the thermal treatment chamber using an elevator mechanism coupled to the carrier, and moving the carrier such that the first slot is in a position adjacent to the transfer opening using the elevator mechanism within a carrier transfer time period and transferring the first substrate out of the thermal treatment chamber at a determined time period for anneal.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: October 29, 2019
    Assignee: Applied Materials, Inc.
    Inventors: James Hoffman, Atsushi Kitani, Hsin-Hsien Wu, Chia-Hung Chen
  • Patent number: 10435812
    Abstract: Methods are provided for generating a crystalline material. The methods comprise depositing a textured thin film in a growth seed area, wherein the textured thin film has a preferential crystallographic axis; providing a growth channel extending from the growth seed area, the growth channel permitting guided lateral growth; and growing a crystalline material in the growth channel along a direction that is substantially perpendicular to the preferential crystallographic axis of the textured thin film. A preferred crystalline material is gallium nitride, and preferred textured thin films are aluminum nitride and titanium nitride.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 8, 2019
    Assignee: Yale University
    Inventor: Jung Han
  • Patent number: 10246773
    Abstract: A method for forming an amorphous thin film comprises: forming a seed layer on a surface of a base by supplying aminosilane-based gas on the base; forming the first boron-doped amorphous thin film by supplying the first source gas including boron-based gas on the seed layer; and forming the second boron-doped amorphous thin film by supplying the second source gas including boron-based gas on the first amorphous thin film.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 2, 2019
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo Shin, Cha-Young Yoo, Woo-Duck Jung, Ho-Min Choi, Wan-Suk Oh, Koon-Woo Lee, Hyuk-Lyong Gwon, Ki-Ho Kim
  • Patent number: 10094024
    Abstract: A method for forming a release layer which lies between a substrate and a supporting member and has a property that changes when the release layer absorbs light coming through the supporting member, by carrying out plasma CVD with a high-frequency power that is set so as to be higher than a power at which a mode jump occurs.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 9, 2018
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yasushi Fujii, Tatsuhiro Mitake, Atsushi Matsushita
  • Patent number: 10076896
    Abstract: A method and system for connecting a plurality of materials using pressure and curing is disclosed. The method provides for: a) receiving the plurality of materials on the vacuum conveyor; b) conveying the received plurality of materials from the first location to a second location along the vacuum conveyor; c) applying a predetermined vacuum pressure; and d) curing the compressed plurality of materials. The system comprises a vacuum conveyor for receiving the plurality of materials at a first location, a moving belt adaptively positioned above the vacuum conveyor at a second location and the vacuum conveyor and the moving belt are arranged to be driven in a predetermined relation to one another, a vacuum pressure source for applying a predetermined vacuum pressure creating a force compressing the plurality of materials; and a curing source at a second location for curing the compressed plurality of materials.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 18, 2018
    Assignee: ALTA DEVICES, INC.
    Inventor: Khurshed Sorabji
  • Patent number: 10014324
    Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: July 3, 2018
    Assignee: Sony Corporation
    Inventor: Akiko Honjo
  • Patent number: 9954071
    Abstract: A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 24, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Yuqiang Ding, Chao Zhao, Jinjuan Xiang
  • Patent number: 9935201
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: April 3, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9922824
    Abstract: A method of forming a silicon film on a target surface of a target object, including: performing a gas process on the target surface of the target object using an oxygen gas and a hydrogen gas; forming the silicon film on the target surface to which the gas process has been performed, wherein the performing a gas process and the forming the silicon film are performed within a single processing chamber.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 20, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 9905444
    Abstract: Embodiments described herein generally relate to apparatus for heating substrates. The apparatus generally include a process chamber having a substrate support therein. A plurality of lamps is positioned to provide radiant energy through an optically transparent dome to a substrate positioned on the substrate support. A light focusing assembly is positioned within the chamber to influence heating and temperature distribution on the substrate and to facilitate formation of a film on a substrate having uniform properties, such as density. The light focusing assembly can include one or more reflectors, light pipes, or refractive lenses.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 27, 2018
    Assignee: Applied Materials, Inc.
    Inventor: Joseph M. Ranish
  • Patent number: 9691881
    Abstract: The invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a protective layer which is above the gate electrode and has a first recess and a second recess; wet etching the active material layer by using the protective layer as a mask to form an active layer; removing a portion of the protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 27, 2017
    Assignees: INNOCOM TECHNOLOGY (SHENZHEN) CO., LTD., INNOLUX CORPORATION
    Inventor: Kuan-Feng Lee
  • Patent number: 9646876
    Abstract: A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 9, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Deenesh Padhi, Srinivas Guggilla, Alexandros T. Demos, Bhaskar Kumar, He Ren, Priyanka Dash
  • Patent number: 9481567
    Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Shi Wang, Yu-Jui Chen, Ting-Ying Chien, Jen-Hao Liu, Ren-Dou Lee
  • Patent number: 9401402
    Abstract: An object of the present invention is to provide a nitride semiconductor device and a nitride semiconductor substrate in each of which a nitride semiconductor layer formed on a silicon substrate is improved in crystallinity to realize a decrease in on-resistance of a field-effect transistor. The nitride semiconductor device includes a silicon substrate, and a first nitride semiconductor layer formed over the silicon substrate and including a nitride semiconductor, wherein a Si <111> axial direction of the silicon substrate is different from a <0001> axial direction of the first nitride semiconductor layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 26, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinichi Kohda, Masahiro Ishida
  • Patent number: 9305794
    Abstract: An etching method is disclosed. A substrate is provided. An etching is performed to form at least one opening in the substrate. An auxiliary etching layer is formed in the opening to cover at least one etching residue. The auxiliary etching layer includes a media, a carrier and an etching component encapsulated by the carrier. A treatment process is performed to the auxiliary etching layer. The treatment process includes applying an energy to the auxiliary etching layer or exposing the auxiliary layer to a gas, so that the carrier breaks in the treatment and thereby the etching component is released to etch the etching residue.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 5, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Ta-Hone Yang
  • Patent number: 9257275
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first layer containing boron and a halogen group by supplying a first precursor gas containing boron and the halogen group to the substrate; and forming a second layer containing the predetermined element, boron, carbon, and nitrogen by supplying a second precursor gas containing the predetermined element and an amino group to the substrate and modifying the first layer.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 9, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
  • Patent number: 8980682
    Abstract: Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren
  • Patent number: 8975134
    Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik, Xuena Zhang
  • Patent number: 8937000
    Abstract: A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (10) of a rotating-disc reactor and directed downwardly onto a wafer carrier (32) and substrates (40) which are maintained at an elevated substrate temperature, typically above about 400° C. and normally about 700-1100° C. to deposit a compound such as a III-V semiconductor. The gases are introduced into the reactor at an inlet temperature desirably above about 75° C. and most preferably about 100°-350° C. The walls of the reactor may be at a temperature close to the inlet temperature. Use of an elevated inlet temperature allows the use of a lower rate of rotation of the wafer carrier, a higher operating pressure, lower flow rate, or some combination of these.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 20, 2015
    Assignee: Veeco Instruments Inc.
    Inventors: Alex Gurary, Mikhail Belousov, Bojan Mitrovic
  • Patent number: 8906790
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Patent number: 8890115
    Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Eli Anguelova Sutter, Peter Werner Sutter
  • Patent number: 8884297
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8822290
    Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Meng-Ku Chen, Huicheng Chang
  • Patent number: 8815711
    Abstract: A manufacturing apparatus for a semiconductor device, including: a reaction chamber configured to perform film formation on a wafer; a process gas supplying mechanism provided in an upper part of the reaction chamber and configured to introduce process gas to an interior of the reaction chamber; a gas discharging mechanism provided in a lower part of the reaction chamber and configured to discharge gas from the reaction chamber; a supporting member configured to hold the wafer; a cleaning gas supplying mechanism provided in an outer periphery of the supporting member and configured to emit cleaning gas in an outer periphery direction below an upper end of the supporting member; a heater configured to heat the wafer; and a rotary driving mechanism configured to rotate the wafer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: August 26, 2014
    Assignees: NuFlare Technology, Inc., Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Kunihiko Suzuki, Hideki Ito, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito
  • Patent number: 8759157
    Abstract: A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 24, 2014
    Assignee: Spansion LLC
    Inventor: Masanori Onodera
  • Patent number: 8709863
    Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: William Hunks, Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Matthias Stender, Philip S. H. Chen, Gregory T. Stauf, Bryan C. Hendrix
  • Patent number: 8670475
    Abstract: Singlet oxygen metastables can be formed. A catalytic coating is formed on an interior surface of a flow reactor, and an oxygen containing species is flowed into the flow reactor to produce singlet oxygen metastables by a chemical reaction in the presence of the catalytic coating.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 11, 2014
    Assignee: Physical Sciences, Inc.
    Inventors: W. Terry Rawlins, Seonkyung Lee, Steven J. Davis
  • Patent number: 8669164
    Abstract: Microelectronic structures and devices, and method of fabricating a three-dimensional microelectronic structure is provided, comprising passing a first precursor material for a selected three-dimensional microelectronic structure into a reaction chamber at temperatures sufficient to maintain said precursor material in a predominantly gaseous state; maintaining said reaction chamber under sufficient pressures to enhance formation of a first portion of said three-dimensional microelectronic structure; applying an electric field between an electrode and said microelectronic structure at a desired point under conditions whereat said first portion of a selected three-dimensional microelectronic structure is formed from said first precursor material; positionally adjusting either said formed three-dimensional microelectronic structure or said electrode whereby further controlled growth of said three-dimensional microelectronic structure occurs; passing a second precursor material for a selected three-dimensional mi
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: March 11, 2014
    Assignee: Los Alamos National Security, LLC
    Inventors: James L. Maxwell, Chris R. Rose, Marcie R. Black, Robert W. Springer
  • Patent number: 8617970
    Abstract: The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: December 31, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Makoto Koto
  • Publication number: 20130337639
    Abstract: The present invention relates to a method for producing a modified surface of a substrate that stimulates the growth of epitaxial layers of group-III nitride semiconductors with substantially improved structural perfection and surface flatness. The modification is conducted outside or inside a growth reactor by exposing the substrate to a gas-product of the reaction between hydrogen chloride (HCl) and aluminum metal (Al). As a single-step or an essential part of the multi-step pretreatment procedure, the modification gains in coherent coordination between the substrate and group-III nitride epitaxial structure to be deposited. Along with epilayer, total epitaxial structure may include buffer inter-layer to accomplish precise substrate-epilayer coordination.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 19, 2013
    Applicant: OSTENDO TECHNOLOGIES, INC.
    Inventors: Vladimir Ivantsov, Anna Volkova, Lisa Shapovalov, Alexander Syrkin, Philippe Spiberg, Hussein S. El-Ghoroury
  • Patent number: 8609519
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Publication number: 20130330916
    Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Daniel T. Pham, Robert J. Miller, Kingsuk Maitra
  • Patent number: 8502191
    Abstract: A semiconductor device includes: a silicon layer (12); an intermediate silicide layer (28) that is provided on the silicon layer (12), has openings, and includes barium silicide; and an upper silicide layer (14) that covers the intermediate silicide layer (28), is positioned to be in contact with the silicon layer (12) through the openings, has a higher dopant concentration than the dopant concentration of the intermediate silicide layer (28), and includes barium silicide.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 6, 2013
    Assignees: University of Tsukuba, Tohoku University
    Inventors: Takashi Suemasu, Noritaka Usami
  • Patent number: 8497192
    Abstract: A method of manufacturing a semiconductor device includes conveying a first substrate provided with an opposing surface having insulator regions and a semiconductor region exposed between the insulator regions and a second substrate provided with an insulator surface exposed toward the opposing surface of the first substrate, into a process chamber in a state that the second substrate is arranged in to face the opposing surface of the first substrate, and selectively forming a silicon-containing film with a flat surface at least on the semiconductor region of the opposing surface of the first substrate by heating an inside of the process chamber and supplying at least a silicon-containing gas and a chlorine-containing gas into the process chamber.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: July 30, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kiyohisa Ishibashi, Atsushi Moriya, Takaaki Noda, Kiyohiko Maeda
  • Patent number: 8486777
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo
  • Patent number: 8455346
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shinichi Nakao, Kei Watanabe, Kazuhiko Yamamoto, Ichiro Mizushima, Yoshio Ozawa
  • Publication number: 20130056770
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 7, 2013
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Publication number: 20130059430
    Abstract: An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.
    Type: Application
    Filed: October 30, 2012
    Publication date: March 7, 2013
    Applicant: Crystal Solar, Incorporated
    Inventor: Crystal Solar, Incorporated
  • Publication number: 20130056742
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Application
    Filed: May 6, 2011
    Publication date: March 7, 2013
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Patent number: 8389345
    Abstract: To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes: a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: March 5, 2013
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Hiroshi Tanabe
  • Patent number: 8389387
    Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: March 5, 2013
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Eli Anguelova Sutter, Peter Werner Sutter
  • Publication number: 20130052808
    Abstract: A method is provided for forming a semiconductor device. The method includes providing a substrate on a substrate holder in a process chamber, where the substrate contains a raised feature having a top surface and a sidewall surface, and flowing a process gas into the process chamber, where the process gas contains a hydrocarbon gas, an oxygen-containing gas, and optionally argon or helium. The method further includes maintaining a process gas pressure of at least 1 Torr in the process chamber, forming a plasma from the process gas using a microwave plasma source, and exposing the substrate to the plasma to deposit a conformal amorphous carbon film over the surfaces of the raised feature.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Publication number: 20130052757
    Abstract: Methods for optimizing a plasma process are provided. The method may include obtaining a measurement spectrum from a plasma reaction in a chamber, calculating a normalized measurement standard and a normalized measurement spectrum of the measurement spectrum, comparing the normalized measurement spectrum with a normalized reference spectrum, and comparing the normalized measurement standard with a normalized reference standard to determine whether to change a process parameter of the plasma process or clean the chamber when the normalized measurement spectrum and the normalized reference spectrum are mismatched.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sangwuk Park, Kye Hyun Baek, Kyoungsub Shin, Brad H. Lee
  • Publication number: 20130029477
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Application
    Filed: September 21, 2012
    Publication date: January 31, 2013
    Applicants: GENITECH, INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
  • Publication number: 20130029479
    Abstract: The invention relates to a multilayer body arrangement, which comprises at least two multilayer bodies each having at least one surface to be processed as well as at least one device for positioning the multilayer bodies, wherein the device is configured such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs. It further relates to a system for processing multilayer bodies with such a multilayer body arrangement, as well as a method for processing multilayer bodies, wherein the multilayer bodies are disposed such that the respective surfaces to be processed are opposite each other and thus form a quasi-closed processing space disposed between the surfaces, in which the processing occurs.
    Type: Application
    Filed: February 22, 2011
    Publication date: January 31, 2013
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Stefan Jost, Joerg Palm, Martin Fuerfanger
  • Publication number: 20130023080
    Abstract: A chemical vapor deposition (CVD) method includes forming a first semiconductor layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a second semiconductor layer on the first semiconductor layer at a second process temperature. Also, a method of manufacturing a light-emitting device (LED) includes: forming a quantum well layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a quantum barrier layer on the quantum well layer at a second process temperature.
    Type: Application
    Filed: January 25, 2012
    Publication date: January 24, 2013
    Inventors: Bum-joon KIM, Ki-sung Kim, Young-sun Kim, Doek-gil Ko, Jin-young Lim, Eui-joon Jeong