Epitaxial Deposition Of Group Iv Elements, E.g., Si, Ge, C (epo) Patents (Class 257/E21.102)
  • Patent number: 10466908
    Abstract: A memory system includes a first buffer memory, a second buffer memory having a higher memory performance rating than the first buffer memory, a nonvolatile semiconductor memory unit including an array of memory cell regions, and a control unit configured to cause data to be buffered in one of the first and second buffer memories before the data are written in the nonvolatile semiconductor memory unit, according to characteristics of the data.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: November 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Akinori Harasawa, Yoshihisa Kojima
  • Patent number: 10234281
    Abstract: A method for evaluating a haze of a substrate surface by a particle counter apparatus using scattering light, the method including calibrating a haze value with the use of a standard sample at the time of obtaining the haze value of the substrate surface from scattering light intensity of light which is entered on the substrate surface, and by using a sample having standard particles applied thereto as the standard sample. Consequently, the method for evaluating a haze by which a haze value of the particle counter apparatus can be calibrated with the use of the standard sample for a haze and a measurement accuracy of the haze can be improved.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 19, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hisayuki Saito
  • Patent number: 10199220
    Abstract: One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alexander Reznicek, Dominic J. Schepis, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi
  • Patent number: 9984875
    Abstract: A method of forming a silicon film, a germanium film or a silicon germanium film on a target substrate having a fine recess formed on a surface of the target substrate by a chemical vapor deposition method includes placing the target substrate having the fine recess in a processing container, and supplying a film forming gas containing an element constituting a film to be formed and a chlorine-containing compound gas into the processing container. Adsorption of the film forming gas at an upper portion of the fine recess is selectively inhibited by the chlorine-containing compound gas.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: May 29, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuya Takahashi, Mitsuhiro Okada, Katsuhiko Komori
  • Patent number: 9653640
    Abstract: MOSFET phototransistors, methods of operating the MOSFET phototransistors and methods of making the MOSFET phototransistors are provided. The phototransistors have a buried electrode configuration, which makes it possible to irradiate the entire surface areas of the radiation-receiving surfaces of the phototransistors.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 16, 2017
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo
  • Patent number: 9018065
    Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joanna Wasyluk, Yew Tuck Chow, Stephan Kronholz, Lindarti Purwaningsih, Ines Becker
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8963124
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Patent number: 8946064
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
  • Patent number: 8928126
    Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 8900978
    Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Nicolas Loubet, Douglas LaTulipe, Alexander Reznicek
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8809947
    Abstract: In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate. The method etches the semiconductor substrate to form a non-planar transistor structure having sidewalls. On a standard (100) <110> substrate the fin sidewalls have (110) surface plane if the fins are aligned or perpendicular with the <110> wafer notch. The method includes depositing a sacrificial liner along the sidewalls of the non-planar transistor structure. Further, a confining material is deposited overlying the semiconductor substrate and adjacent the sacrificial liner. The method includes removing at least a portion of the sacrificial liner and forming a void between the sidewalls of the non-planar transistor structure and the confining material. A cladding layer is epitaxially grown in the void. Since the sidewall growth is limited by the confining material, a cladding layer of uniform thickness is enabled on fins with (110) sidewall and (100) top surface.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 19, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Kerem Murat Akarvardar, Ajey Poovannummoottil Jacob
  • Patent number: 8759844
    Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 24, 2014
    Inventor: Shinya Iwasa
  • Patent number: 8759233
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Hoon Cho
  • Patent number: 8652937
    Abstract: A back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate is disclosed. The device includes an insulator layer, a semiconductor substrate having an interface with the insulator layer, an epitaxial layer grown on the semiconductor substrate; and one or more imaging components in the epitaxial layer. The semiconductor substrate and the epitaxial layer exhibit a net doping concentration profile having a maximum value at a predetermined distance from the interface which decreases monotonically on both sides of the profile. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 18, 2014
    Assignee: SRI International
    Inventors: Levine Peter Alan, Pradyumna Swain, Mahalingam Bhaskaran
  • Publication number: 20130302973
    Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Joanna Wasyluk, Yew Tuck Chow, Stephan Kronholz, Lindarti Purwaningsih, Ines Becker
  • Patent number: 8530340
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: September 10, 2013
    Assignee: ASM America, Inc.
    Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Patent number: 8524582
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 3, 2013
    Assignee: The Arizona Board of Regents
    Inventors: John Kouvetakis, Cole J. Ritter, III
  • Patent number: 8518360
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: August 27, 2013
    Inventors: John Kouvetakis, Cole J. Ritter, III, Changwu Hu, Ignatius S. T. Tsong, Andrew Chizmeshya
  • Patent number: 8501600
    Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Errol Sanchez, Yi-Chiau Huang, David K. Carlson
  • Patent number: 8497217
    Abstract: A film forming apparatus and a film forming method for suppressing a drop in the film forming speed caused by-product gas are provided. A film forming apparatus for forming a film on a wafer includes a chamber in which the wafer is located; a gas introducing member configured to introduce raw material gas into the chamber, in which the raw material gas turning into by-product gas and a substance which adheres to the surface of the wafer by reacting at a surface of the wafer; and a reverse reaction member configured to generate the raw material gas by causing the by-product gas to react in the chamber.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 30, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takahiro Ito, Kenji Nakashima
  • Patent number: 8492245
    Abstract: Methods for making growth templates for the epitaxial growth of compound semiconductors and other materials are provided. The growth templates are thin layers of single-crystalline materials that are themselves grown epitaxially on a substrate that includes a thin layer of sacrificial material. The thin layer of sacrificial material, which creates a coherent strain in the single-crystalline material as it is grown thereon, includes one or more suspended sections and one or more supported sections.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 23, 2013
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Max G. Lagally, Deborah M. Paskiewicz, Boy Tanto
  • Publication number: 20130168697
    Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 4, 2013
    Applicant: TOKAI CARBON KOREA CO., LTD.
    Inventors: Joung Il Kim, Jae Seok Lim, Mi-Ra Yoon
  • Publication number: 20130105861
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Publication number: 20130105796
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.
    Type: Application
    Filed: October 16, 2012
    Publication date: May 2, 2013
    Inventors: JIQUAN LIU, SHENGAN XIAO, WEI JI
  • Publication number: 20130102132
    Abstract: A method of manufacturing a semiconductor device includes: accommodating a substrate in a processing chamber; and supplying an organosilicon-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. In the forming of the film including silicon and carbon, a cycle is performed a predetermined number of times. The cycle includes supplying the organosilicon-based gas into the processing chamber and confining the organosilicon-based gas in the processing chamber, maintaining a state in which the organosilicon-based gas is confined in the processing chamber, and exhausting an inside of the processing chamber.
    Type: Application
    Filed: September 26, 2012
    Publication date: April 25, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Hitachi Kokusai Electric Inc
  • Publication number: 20130084693
    Abstract: A thin film forming method which forms a seed film and an impurity-containing silicon film on a surface of an object to be processed in a processing container configured to be vacuum exhaustible includes: performing a first step which forms the seed film by supplying a seed film raw material gas including at least any one of an aminosilane-based gas and a higher silane into the processing container; and performing a second step which forms the impurity-containing silicon film in an amorphous state by supplying a silane-based gas and an impurity-containing gas into the processing container.
    Type: Application
    Filed: September 27, 2012
    Publication date: April 4, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akinobu KAKIMOTO, Atsushi ENDO, Takahiro MIYAHARA, Shigeru NAKAJIMA, Satoshi TAKAGI, Kazumasa IGARASHI
  • Publication number: 20130065349
    Abstract: A method for forming a photodetector device includes forming waveguide feature on a substrate, and forming a photodetector feature including a germanium (Ge) film, the Ge film deposited on the waveguide feature using a plasma enhanced chemical vapor deposition (PECVD) process, the PECVD process having a deposition temperature from about 500° C. to about 550° C., and a deposition pressure from about 666.612 Pa to about 1066.579 Pa.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Pratik P. Joshi, Deborah A. Neumayer
  • Publication number: 20130040438
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Patent number: 8372671
    Abstract: Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8373233
    Abstract: A semiconductor device includes a gate, a source region and a drain region that are co-doped to produce a strain in the channel region of a transistor. The co-doping can include having a source and drain region having silicon that includes boron and phosphorous or arsenic and gallium. The source and drain regions can include co-dopant levels of more than 1020 atom/cm3. The source region and drain region each can be co-doped with more boron than phosphorous or can be co-doped with more phosphorous than boron. Alternatively, the source region and drain region each can be co-doped with more arsenic than gallium or can be co-doped with more gallium than arsenic. A method of manufacturing a semiconductor device includes forming a gate on top of a substrate and over a nitrogenated oxide layer, etching a portion of the substrate and nitrogenated oxide layer to form a recessed source region and a recessed drain region, filling the recessed source region and the recessed drain region with a co-doped silicon compound.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: February 12, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Zhiyuan Ye
  • Publication number: 20130017674
    Abstract: Described herein are methods for forming a semiconductor structure. The methods involve forming a doped semiconductor film, amorphizing the doped semiconductor film through ion implantation; and annealing the doped semiconductor film. The ion implantation and the annealing can increase an activation efficiency of the dopant. The ion implantation and the annealing can also reduce a number of crystalline defects in the doped semiconductor film.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Hiroshi Itokawa
  • Patent number: 8354282
    Abstract: An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiNX<1.33), that provides optimal refractive index matching between sapphire and silicon. A one quarter wavelength, magnesium fluoride (?/4-MgF2) antireflective layer deposited on the back surface of the thinned sapphire provides refractive index matching at the air-sapphire interface. Selecting a composition of x=0.62 for a-SiNX, tunes an optimal refractive index for the layer. Selecting design thicknesses of 52 nm for single crystal AlN, 30 nm for a-SiN0.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 15, 2013
    Inventor: Alvin Gabriel Stern
  • Patent number: 8329532
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Patent number: 8309986
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20120244688
    Abstract: Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and/or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 27, 2012
    Applicant: ASM AMERICA, INC.
    Inventors: Matthias Bauer, Keith Doran Weeks
  • Patent number: 8273664
    Abstract: A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and middle SiN of the sandwich layer; tilling the deep trenches with epitaxial film or polysilicon film; polishing the wafer to get a planarized surface by stopping at the surface of the bottom oxide layer; removing the bottom oxide layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 25, 2012
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Xiaohua Cheng, Shengan Xiao
  • Patent number: 8268665
    Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.
    Type: Grant
    Filed: June 26, 2011
    Date of Patent: September 18, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: William Hunks, Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Matthias Stender, Philip S. H. Chen, Gregory T. Stauf, Bryan C. Hendrix
  • Publication number: 20120231615
    Abstract: Substrates are mounted on a plurality of susceptors respectively. The plurality of susceptors on which respective substrates are mounted are placed on a rotational mechanism so that the susceptors are vertically spaced at a predetermined interval. The rotational mechanism on which the plurality of susceptors are placed is rotated. The plurality of susceptors on which the substrates are mounted respectively are heated. Semiconductor thin-films are deposited by supplying a source gas to each of the susceptors that are heated while being rotated, the source gas having been heated while passing through gas flow paths of respective path lengths substantially equal to each other.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 13, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yasuhiko Senda, Satomi Itoh, Kazuhiro Fujikawa, Shigeki Shimada, Jun Genba, Takemi Terao, Masaru Furusho
  • Publication number: 20120216743
    Abstract: A downsized substrate may be housed in a substrate accommodation vessel (FOUP) constituting a transfer system corresponding to a large diameter substrate. An attachment includes an upper plate and a lower plate supported by a first support groove that can support an 8-inch wafer, and holding columns installed at the upper plate and the lower plate and including a second support groove that can support a 2-inch wafer (if necessary, via a wafer holder and a holder member). Accordingly, the 2-inch wafer can be housed in a pod corresponding to the 8-inch wafer, and the pod, which is a transfer system, can be standardized to reduce cost of a semiconductor manufacturing apparatus. In addition, a distance from each gas supply nozzle to the wafer can be increased to sufficiently mix reactive gases before arrival at the wafer and improve film-forming precision to the wafer.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takeshi Itoh, Akinori Tanaka
  • Publication number: 20120193632
    Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.
    Type: Application
    Filed: January 24, 2012
    Publication date: August 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Satoshi TORIUMI
  • Publication number: 20120193636
    Abstract: An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiNX<1.33), that provides optimal refractive index matching between sapphire and silicon. A one quarter wavelength, magnesium fluoride (?/4-MgF2) antireflective layer deposited on the back surface of the thinned sapphire provides refractive index matching at the air-sapphire interface. Selecting a composition of x=0.62 for a-SiNX, tunes an optimal refractive index for the layer. Selecting design thicknesses of 52 nm for single crystal AlN, 30 nm for a-SiN0.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Inventor: Alvin Gabriel Stern
  • Publication number: 20120193633
    Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate (11a) in a chamber (26); (b) supplying a microwave into the chamber (26) through a dielectric plate (24), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film (14) with an aluminum concentration of 1.0×1016 atoms/cm3 or less on the substrate (11a) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm2/Vs as its active layer is obtained.
    Type: Application
    Filed: September 21, 2010
    Publication date: August 2, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihiko Kohno, Toshio Mizuki, Kohichi Tanaka
  • Publication number: 20120187419
    Abstract: The invention relates to a production method for a unipolar semiconductor component having a drift layer (16), comprising the following step: forming the drift layer (16) with a continuously decreasing concentration of a charge carrier doping (n) along the growth direction (19) of the drift layer (16) by way of epitaxial precipitation of the material of the drift layer (16), which comprises at least one wide band gap material. By using silicon carbide for the drift layer (16) formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping (n) due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer (16), which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner.
    Type: Application
    Filed: July 12, 2010
    Publication date: July 26, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Rudolf Elpelt, Peter Friedrichs
  • Publication number: 20120184054
    Abstract: Provided is a semiconductor manufacturing apparatus including: a reaction chamber including a gas supply inlet and a gas exhaust outlet, and into which a wafer is to be introduced; a process gas supply mechanism that supplies process gas into the reaction chamber from the gas supply inlet of the reaction chamber; a wafer retaining member that is arranged in the reaction chamber and that retains the wafer; a heater that heats the wafer retained by the wafer retaining member to a predetermined temperature; a rotation drive control mechanism that rotates the wafer retaining member together with the wafer; a gas exhaustion mechanism that exhausts gas in the reaction chamber from the gas exhaust outlet of the reaction chamber; and a drain that is disposed at a bottom portion near a wall surface in the reaction chamber and that collects and discharges oily silane that drips from the wall surface.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Inventors: Kunihiko SUZUKI, Hironobu HIRATA
  • Publication number: 20120175613
    Abstract: The present invention provides a clean and high-purity polycrystalline silicon mass having a small content of chromium, iron, nickel, copper, and cobalt in total, which are heavy metal impurities that reduce the quality of single-crystal silicon. In the vicinity of an electrode side end of a polycrystalline silicon rod obtained by the Siemens method, the total of the chromium, iron, nickel, copper, and cobalt concentrations is high. Accordingly, before a crushing step of a polycrystalline silicon rod 100, a removing step of removing at least 70 mm of a polycrystalline silicon portion from the electrode side end of the polycrystalline silicon rod 100 extracted to the outside of a reactor is provided. Thereby, the polycrystalline silicon portion in which the total of the chromium, iron, nickel, copper, and cobalt concentrations in a bulk is not less than 150 ppta can be removed.
    Type: Application
    Filed: July 21, 2010
    Publication date: July 12, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shigeyoshi Netsu, Junichi Okada, Fumitaka Kume
  • Patent number: 8216537
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 10, 2012
    Assignee: Arizona Board of Regents
    Inventors: John Kouvetakis, Cole J. Ritter, III, Changwu Hu, Ignatius S. T. Tsong, Andrew Chizmeshya