Abstract: An apparatus for depositing a thin layer and associated method, the apparatus including a process chamber; a support in the process chamber, substrates being supportable on the support at different heights; a gas injector configured to inject a gas into the process chamber; and a heater configured to heat the process chamber, wherein the gas injector includes a first injector configured to inject a first gas; and a second injector configured to inject a second gas, a flow rate of the first gas injected from the first injector ranges from 120 sccm to 240 sccm, and a flow rate of the second gas injected from the second injector ranges from 1,200 sccm to 2,400 sccm.

Abstract: Embodiments of the present invention generally relate to chambers and methods of processing substrates therein. The chambers generally include separate process gas and purge gas regions. The process gas region and purge gas region each have a respective gas inlet and gas outlet. The methods generally include positioning a substrate on a substrate support within the chamber. The plane of the substrate support defines the boundary between a process gas region and purge gas region. Purge gas is introduced into the purge gas region through at least one purge gas inlet, and removed from the purge gas region using at least one purge gas outlet. The process gas is introduced into the process gas region through at least one process gas inlet, and removed from the process gas region through at least one process gas outlet. The process gas is thermally decomposed to deposit a material on the substrate.

Abstract: A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: A back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate is disclosed. The device includes an insulator layer, a semiconductor substrate having an interface with the insulator layer, an epitaxial layer grown on the semiconductor substrate; and one or more imaging components in the epitaxial layer. The semiconductor substrate and the epitaxial layer exhibit a net doping concentration profile having a maximum value at a predetermined distance from the interface which decreases monotonically on both sides of the profile. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device.

Abstract: A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.

Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.

Abstract: Disclosed is a method for producing core-shell nanowires in which an insulating film is previously patterned to block the contacts between nanowire cores and nanowire shells. According to the method, core-shell nanowires whose density and position is controllable can be produced in a simple manner. Further disclosed are nanowires produced by the method and a nanowire device comprising the nanowires. The use of the nanowires leads to an increase in the light emitting/receiving area of the device. Therefore, the device exhibits high luminance/efficiency characteristics.

Abstract: A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.

Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

Abstract: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more imaging components in the epitaxial layer in proximity to a face of the epitaxial layer, the face being opposite the interface of the semiconductor substrate and the insulator layer, the imaging components comprising junctions within the epitaxial layer; wherein the semiconductor substrate and the epitaxial layer exhibit a net doping concentration having a maximum value at a predetermined distance from the interface of the insulating layer and the semiconductor substrate and which decreases monotonically on both sides of the profile from the maximum value within a portion of the semiconductor substrate and the epitaxial layer.

Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.

Abstract: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light emission face of the light emission structure; removing the light shield film corresponding to an area of the light emission face of the light emission structure including and above the first clad layer; and removing the protection layer.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising silicon is provided with an n-type doped semiconductor region (2) comprising silicon by means of an epitaxial deposition process, wherein the epitaxial deposition process of the n-type region is performed by positioning the semiconductor body (1) in an epitaxial reactor and introducing in the reactor a first gas stream comprising a carrier gas and further gas streams comprising a gaseous compound comprising silicon and a gaseous compound comprising an element from the fifth column of the periodic system of elements, while heating the semiconductor body (1) to a growth temperature (Tg) and using an inert gas as the carrier gas. According to the invention for the gaseous compound comprising silicon a mixture is chosen of a first gaseous silicon compound which is free of chlorine and a second gaseous silicon compound comprising chlorine.

Abstract: An apparatus for manufacturing a semiconductor device, including in a reaction chamber: a rotor provided with a holding member holding a wafer thereon and a heater heating the wafer therein; a rotation drive mechanism; a gas supply mechanism; a gas exhaust mechanism; and a rectifying plate for rectifying the supplied process gas to supply the rectified gas, and including: an annular rectifying fin mounted on a lower portion of the plate, having a larger lower end inside diameter than an upper end inside diameter thereof and downward rectifying gas exhausted in an outer circumferential direction from above the wafer; and a distance control mechanism controlling a vertical distance between the plate and the wafer and a vertical distance between the fin and the rotor top face to be predetermined distances, respectively, thereby providing higher film formation efficiency.

Abstract: A semiconductor device with a semiconductor body and method for its production is provided. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

Abstract: A process for producing a semiconductor device, in which in the formation of a boron doped silicon film from, for example, monosilane and boron trichloride by vacuum CVD technique, there can be produced a film excelling in inter-batch homogeneity with respect to the growth rate and concentration of a dopant element, such as boron. The process includes the step of performing the first purge through conducting at least once of while a substrate after treatment is housed in a reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto and the steps of performing the second purge through conducting at least once of after carrying of the substrate after treatment out of the reaction furnace, prior to carrying of a substrate to be next treated into the reaction furnace and while at least no product substrate is housed in the reaction furnace, vacuuming of the reaction furnace and inert gas supply thereto.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the spacer layer.

Abstract: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Abstract: The invention relates to a method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer 1 is produced, in a step subsequent thereto, on the latter an intermediate layer system 2 which has at least one doped partial layer is deposited, in a step subsequent thereto, an absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallisation step, the absorber layer 3 is heated, melted, cooled and tempered. In an advantageous method modification, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied applied on the absorber layer 3.

Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.

Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.

Abstract: A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a channel region. The improvements from the controllability of the placement of the Schottky-barrier junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.