Abstract: A method making it possible to obtain, on an upper surface of a crystalline substrate, a semipolar layer of nitride material comprising any one from among gallium, aluminium or indium, the method comprises the following steps: obtaining, on the upper surface of the crystalline substrate, a plurality of parallel grooves which extend in a first direction, one of the two opposite facets exhibiting a crystal orientation; etching a plurality of parallel slices which extend in a second direction that has undergone a rotation with respect to the first direction of the grooves in such a way as to obtain individual facets exhibiting a crystal orientation; epitaxial growth of the material from the individual facets.

Abstract: A growth-rate measuring apparatus has a refractometer to irradiate light of a plurality of different wavelengths to a surface of a substrate to measure a reflectivity of the surface of the substrate per different wavelengths, a fitter to fit a reflectivity calculated by a model function, the model function being obtained in advance, to a measured value of the reflectivity, for at least one layer of thin films laminated one by one on the substrate, with at least one of a refractive index and a growth rate as a fitting parameter, a parameter extractor to extract sets of fitting parameters for each wavelength in the different wavelengths, respectively, for which an error between the calculated reflectivity and the measured value of the reflectivity is minimum, and a parameter selector to select an optimum set of values of the fitting parameter, among the fitting parameters extracted for the different wavelengths.

Abstract: Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3+NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.

Abstract: A method of manufacturing a vertical structure light emitting diode device, the method including: sequentially forming a first conductivity type III-V group compound semiconductor layer, an active layer, and a second conductivity type III-V group compound semiconductor layer on a substrate for growth; bonding a conductive substrate to the second conductivity type III-V group compound semiconductor layer; removing the substrate for growth from the first conductivity type III-V group compound semiconductor layer; and forming an electrode on an exposed portion of the first conductive III-V group compound semiconductor layer due to the removing the substrate for growth, wherein the bonding a conductive substrate comprises partially heating a metal bonding layer by applying microwaves to a bonding interface while bringing the metal bonding layer into contact with the bonding interface.

Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.

Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.

Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes forming an aluminum oxide coating on the surface of the silicon substrate, the aluminum oxide being substantially crystal lattice matched to the surface of the silicon substrate and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide coating substantially crystal lattice matched to the surface of the aluminum nitride.

Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate, each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.

Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate , each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.

Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).

Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.

Abstract: Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates (10) in which the deviation in crystallographic plane orientation in any given point on the major face (10m) of the crystal plates (10), with respect to an {hkil} plane chosen exclusive of the {0001} form, is not greater than 0.5°; arranging the plurality of crystal plates (10) in a manner such that the plane-orientation deviation, with respect to the {hkil} plane, in any given point on the major-face (10m) collective surface (10a) of the plurality of crystal plates (10) will be not greater than 0.5°, and such that at least a portion of the major face (10m) of the crystal plates (10) is exposed; and growing second III-nitride crystal (20) onto the exposed areas of the major faces (10m) of the plurality of crystal plates (10).

Abstract: Affords AlxGa(1-x)As (0?x?1) substrates epitaxial wafers for infrared LEDs, infrared LEDs, methods of manufacturing AlxGa(1-x)As substrates, methods of manufacturing epitaxial wafers for infrared LEDs, and methods of manufacturing infrared LEDs, whereby a high level of transmissivity is maintained, and through which, in the fabrication of semiconductor devices, the devices prove to have superior light output characteristics. An AlxGa(1-x)As substrate (10a) as disclosed is an AlxGa(1-x)As substrate (10a) furnished with an AlxGa(1-x)As layer (11) having a major surface (11a) and, on the reverse side from the major surface (11a), a rear face (11b), and is characterized in that in the AlxGa(1-x)As layer (11), the amount fraction x of Al in the rear face (11b) is greater the amount fraction x of Al in the major surface (11a). The AlxGa(1-x)As substrate (10a) may additionally be provided with a GaAs substrate (13), contacting the rear face (11b) of the AlxGa(1-x)As layer (11).

Abstract: A method includes (a) preparing a substrate, and (b) growing a ZnO-containing compound semiconductor layer above the substrate by supplying at the same time at least Zn and O as source gases and S as a surfactant.

Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: A fabrication method of fabricating a structure capable of being used for generation or detection of electromagnetic radiation includes a forming step of forming a layer containing a compound semiconductor on a substrate at a substrate temperature below about 300° C., a first heating step of heating the substrate with the layer in an ambience containing arsenic, and a second heating step of heating the substrate with the layer at the substrate temperature above about 600° C. in a gas ambience incapable of chemically reacting on the compound semiconductor. Structures of the present invention capable of being used for generation or detection of electromagnetic radiation can be fabricated using the fabrication method by appropriately regulating the substrate temperature, the heating time, the gas ambience and the like in the second heating step.

Abstract: A method of MBE growth of a semiconductor layer structure comprises growing a first (Al,Ga)N layer (step 13) over a substrate at the first substrate temperature (T1) using ammonia as the nitrogen precursor. The substrate is then cooled (step 14) to a second-substrate temperature (T2) which is lower than the first substrate temperature. An (In,Ga)N quantum well structure is then grown (step 15) over the first (Al,Ga)N layer by MBE using ammonia as the nitrogen precursor. The supply of ammonia to the substrate is maintained continuously during the first growth step, the cooling step, and the second growth step. After completion of the growth of the (In,Ga)N quantum well structure, the substrate may be heated to a third temperature (T3) which is greater than the second substrate temperature (T2). A second (Al,Ga)N layer is then grown over the (In,Ga)N quantum well structure (step 17).

Abstract: A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices.

Abstract: Provided is a nitride-based semiconductor light emitting device having increased efficiency and power characteristics and method of manufacturing the same. The method may include forming a sacrificial layer on a substrate, forming a passivation layer on the sacrificial layer, forming a plurality of masking dots of a metal nitride on the passivation layer, laterally epitaxially growing a nitride-based semiconductor layer on the passivation layer using the masking dots as masks, forming a semiconductor device on the nitride-based semiconductor layer, and wet etching the sacrificial layer to separate and/or remove the substrate from the semiconductor device.

Abstract: A method for removing a mask in a selective area epitaxy process is provided. The method includes forming a first layer on a substrate and oxidizing the first layer. A patterned photoresist can be formed on the oxidized first layer. A portion of the oxidized first layer can then be removed using a wet chemical etch to form a mask. After removing the patterned photoresist a second layer can be epitaxially grown in a metal organic chemical vapor deposition (MOCVD) chamber or a chemical beam epitaxy (CBE) chamber on a portion of the first layer exposed by the mask. The mask can then be removed the mask in the MOCVD/MBE chamber. The disclosed in-situ mask removal method minimizes both the atmospheric exposure of a growth surface and the number of sample transfers.