Abstract: The present disclosure provides a method for facet-selective passivation on each crystal facet of colloidal nanocrystals via solution-phase ligand exchange process, thereby providing highly-passivated and colloidally-stable nanocrystal inks. This ligand exchange strategy separately addresses polar and non-polar facets precluding from deleterious nanocrystal aggregation in the colloid. The method involves the introduction of alkali metal organic complexes during metal halide conventional solution exchanges, and one specific example is Na+·Ac?. Alkali metal ions stabilize and passivate non polar facets whereas polar facets are passivated through metal halides. This strategy leads to a significant decrease in nanocrystal aggregation during and after ligand exchange, and to improved photophysical properties stemming from this. The resulting nanocrystal solid films exhibit improved stability, retain their absorption features, and have a minimized Stokes shift.

Abstract: There is provided a method of manufacturing a crystal substrate, including: preparing a first crystal body which is a substrate comprising a single crystal of group III nitride produced by a vapor phase method and having a first main surface, and in which c-plane of the single crystal is curved in a concave spherical shape with a predetermined curvature; and growing a second crystal body comprising a single crystal of group III nitride on the first main surface, in a mixed melt containing an alkali metal and a group III element.

Abstract: According to the present invention, there is provided a group III nitride semiconductor substrate (free-standing substrate 30) that is formed of group III nitride semiconductor crystals. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A variation coefficient of an emission wavelength of each of the first and second main surfaces, which is calculated by dividing a standard deviation of an emission wavelength by an average value of the emission wavelength, is 0.05% or less in photoluminescence (PL) measurement in which mapping is performed in units of an area of 1 mm2 by emitting helium-cadmium (He—Cd) laser, which has a wavelength of 325 nm and an output of 10 mW or more and 40 mW or less, at room temperature. In a case where devices are manufactured over the free-standing substrate 30, variations in quality among the devices are suppressed.

Abstract: Hydride phase vapor epitaxy (HVPE) growth apparatus, methods and materials and structures grown thereby. An HVPE reactor includes generation, accumulation, and growth zones. A source material for growth of indium nitride is generated and collected inside the reactor. A first reactive gas reacts with an indium source inside the generation zone to produce a first gas product having an indium-containing compound. The first gas product is cooled and condenses into a liquid or solid condensate or source material having an indium-containing compound. The source material is collected in the accumulation zone. Vapor or gas resulting from evaporation of the condensate forms a second gas product, which reacts with a second reactive gas in the growth zone for growth of indium nitride.

Abstract: A substrate processing system includes a first chamber including a substrate support. A showerhead is arranged above the first chamber and is configured to filter ions and deliver radicals from a plasma source to the first chamber. The showerhead includes a heat transfer fluid plenum, a secondary gas plenum including an inlet to receive secondary gas and a plurality of secondary gas injectors to inject the secondary gas into the first chamber, and a plurality of through holes passing through the showerhead. The through holes are not in fluid communication with the heat transfer fluid plenum or the secondary gas plenum.

Abstract: Devices for the separation of components within a fluid are disclosed herein. The device typically includes layers of spacers and separation surfaces. The separation panels have channels with functionalized surfaces to attract and retain components within the fluid. The separation panels include a border (housing) to constrain the fluid.

Abstract: A surface roughening method includes the following steps: preparing a first epitaxial layer of a three-dimensional island shape growth over a light emitting structure; and preparing a discontinuous second epitaxial layer over the first epitaxial layer. The surface roughening method provided in the present application is simple and convenient, and improves the efficiency. In addition to the epitaxial growth process, it is not necessary to use an additional process such as wet etching, photonic crystal and other processes to further process the surface of the epitaxial layer, and the method may be implemented by means of one process in a same reaction equipment.

Abstract: A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.

Abstract: A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

Abstract: A semiconductor structure including a substrate, a buffer layer, a superlattice formed on the buffer layer, the superlattice including a pattern including n layers made of different materials, n being at least equal to 2, each layer including an AlxGayInwBzN type material where x+y+w+z=1, the thickness of each layer being less than the critical thickness thereof, the number of patterns being at least equal to 50, an insert layer wherein the material has a first lattice parameter, a layer of GaN material, wherein the lattice parameter is greater than the first lattice parameter such that the layer of GaN material is compressed by the insert layer.

Abstract: A light emitting diode is provided to include a first conductive-type semiconductor layer; a mesa including a second conductive-type semiconductor layer disposed on the first conductive-type semiconductor layer and an active layer interposed between the first and the second conductive-type semiconductor layers; and a first electrode disposed on the mesa, wherein the first conductive-type semiconductor layer includes a first contact region disposed around the mesa along an outer periphery of the first conductive-type semiconductor layer; and a second contact region at least partially surrounded by the mesa, the first electrode is electrically connected to at least a portion of the first contact region and at least a portion of the second contact region, and a linewidth of an adjoining region between the first contact region and the first electrode is greater than the linewidth of an adjoining region between the second contact region and the first electrode.

Abstract: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response to an electrical bias across said doped layers. A quantum well structure is included that is integral to the emitter structure and has a plurality of layers having a composition and thickness such that the quantum well structure absorbs at least some of the light emitted from the active region and re-emits light of at least one different wavelength of light from said first wavelength.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.

Abstract: A power device manufacturing method is provided. The power device manufacturing method may perform patterning of regions on which a source electrode and a drain electrode are to be formed, may regrow n+-gallium nitride (GaN) and p+-GaN in the patterned regions and thus, a thin film crystal may not be damaged. Also, a doping concentration of n+-GaN or p+-GaN may be adjusted, an ohmic resistance in the source electrode region and the drain electrode region may decrease, and a current density may increase. The power device manufacturing method may regrow n+-GaN and p+-GaN at a high temperature after an n-GaN layer and a p-GaN layer are patterned. Accordingly, a thin film crystal may not be damaged and thus, a reliability may be secured, and an annealing process may not be additionally performed and thus, a process may be simplified and a cost may be reduced.

Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.

Abstract: A method for manufacturing a semiconductor light emitting element (1) which includes a first step of forming a first n-type semiconductor layer (12c) on a substrate (11) and a second step of sequentially forming a regrowth layer (12d) of the first n-type semiconductor layer (12c), a second n-type semiconductor layer (12b), a light emitting layer (13), and a p-type semiconductor layer (14) on the first n-type semiconductor layer (12c). In the step of forming the second n-type semiconductor layer (12b), a step (1) of supplying Si less than that forming the regrowth layer (12d) as a dopant to form a first layer of the second n-type semiconductor layer and a step (2) of supplying the Si more than that in the step (1) to form a second layer of the second n-type semiconductor layer are performed in this order.

Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Abstract: Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4% are provided. Wall plug efficiencies may be at least 5% or at least 6%. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 345 nm with wall plug efficiencies of at least than 2% are also provided. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 330 nm with wall plug efficiencies of at least than 0.4% are provided. Light emitting devices and methods of fabricating light emitting devices having a peak output wavelength of not greater than 360 nm and an output power of at least 5 mW, having a peak output wavelength of 345 nm or less and an output power of at least 3 mW and/or a peak output wavelength of 330 nm or less and an output power of at least 0.3 mW at a current density of less than about 0.35 ?A/?m2 are also provided.

Abstract: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently.

Abstract: The invention relates to a new High Electron Mobility Transistor (HEMT), made essentially of layers of Group XIII element(s) nitride(s). Contrary to currently available transistors of this type, the transistor according to the invention is produced on a homosubstrate made of gallium-containing nitride, has no nucleation layer and its buffer layer is remarkably thinner than in known HEMTs. Preferably, at least the buffer layer, being a part of the transistor according to the present invention, is produced by epitaxial methods and the direction of growth of said layer in an epitaxial process is essentially perpendicular to the direction of growth of the substrate. The invention relates also to a method of manufacturing of High Electron Mobility Transistor (HEMT).

Abstract: Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.

Abstract: Chemical vapor deposition (CVD) systems for forming layers on a substrate are disclosed. Embodiments of the system comprise at least two processing chambers that may be linked in a cluster tool. A first processing chamber provides a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining isolation. A second processing chamber provides a CVD system. Methods of forming layers on a substrate comprise forming one or more layers in each processing chamber. The systems and methods are suitable for preparing Group III-V, Group II-VI or Group IV thin film devices.

Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.

Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

Abstract: A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.

Abstract: A method of manufacturing of a semi-conductor element, comprising the following steps: providing a substrate, the substrate having a surface, the surface being partially coated with a coating and having at least one uncoated area, and growing a truncated pyramid of gallium nitride on the uncoated area, wherein the method comprises the following step: growing at least one gallium nitride column on the truncated pyramid.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an ?-axis direction comprising a 0.15° or greater miscut angle towards the ?-axis direction and a less than 30° miscut angle towards the ?-axis direction.

Abstract: A surface of a sapphire (0001) substrate is processed so as to have recesses and protrusions so that protrusion tops are made flat and have a given plan-view pattern. An initial-stage AlN layer is epitaxially grown on the surface of the sapphire (0001) substrate so that new recesses are formed over the recesses, by performing C axis orientation control so that a C+ axis oriented AlN layer grows on flat surfaces of the protrusion tops, excluding edges. A first ELO layer including an AlN (0001) layer is epitaxially grown on the initial-stage AlN layer by an epitaxial lateral overgrowth method, and stops growing before a recess upper region above the new recesses is completely covered with the first ELO layer that is laterally grown from a protrusion upper surface of the initial-stage AlN layer. A second ELO layer including an AlxGa1-xN (0001) layer (1>x>0) is epitaxially grown on the first ELO layer by an epitaxial lateral overgrowth method.

Abstract: A vertical geometry light emitting diode with a strain relieved superlattice layer on a substrate comprising doped AlXInYGa1-X-YN. A first doped layer is on the strain relieved superlattice layer AlXInYGa1-X-YN and the first doped layer has a first conductivity. A multilayer quantum well is on the first doped layer comprising alternating layers quantum wells and barrier layers. The multilayer quantum well terminates with a barrier layer on each side thereof. A second doped layer is on the quantum well wherein the second doped layer comprises AlXInYGa1-X-YN and said second doped layer has a different conductivity than said first doped layer. A contact layer is on the third doped layer and the contact layer has a different conductivity than the third doped layer. A metallic contact is in a vertical geometry orientation.

Abstract: A method of obtaining a hexagonal würtzite type epitaxial layer with a low impurity concentration of alkali-metal by using a hexagonal würtzite substrate possessing a higher impurity concentration of alkali-metal, wherein a surface of the substrate upon which the epitaxial layer is grown has a crystal plane which is different from the c-plane.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween.

Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.

Abstract: A nitride semiconductor device in which contact resistance between an ohmic electrode and an ohmic recess portion is reduced and a method of manufacturing the nitride semiconductor device are provided. The nitride semiconductor device includes: a first nitride semiconductor layer formed on a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than a bandgap of the first nitride semiconductor layer; an ohmic recess portion formed in at least the second nitride semiconductor layer; and an ohmic electrode provided in contact with the ohmic recess portion. The ohmic recess portion includes a corrugated structure in at least a part of a plane in contact with the ohmic electrode.

Abstract: An AlGaN composition is provided comprising a group III-Nitride active region layer, for use in an active region of a UV light emitting device, wherein light-generation occurs through radiative recombination of carriers in nanometer scale size, compositionally inhomogeneous regions having band-gap energy less than the surrounding material. Further, a semiconductor UV light emitting device having an active region layer comprised of the AlGaN composition above is provided, as well as a method of producing the AlGaN composition and semiconductor UV light emitting device, involving molecular beam epitaxy.

Abstract: Amongst the candidates for very high efficiency solid state lights sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects. Further manufacturing requirements demand reproducible nanowire diameter, length etc to allow these nanowires to be embedded within device structures. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group III—nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. The technique also allows for unique dot-within-a-dot nanowire structures.

Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.

Abstract: Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm?3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle ? of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle ?. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.

Abstract: A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.