Abstract: In a method according to embodiments of the invention, a semiconductor structure including a III-nitride light emitting layer disposed between a p-type region and an n-type region is grown. The p-type region is buried within the semiconductor structure. A trench is formed in the semiconductor structure. The trench exposes the p-type region. After forming the trench, the semiconductor structure is annealed.

Abstract: Provided is a Group III-V compound semiconductor device. The device includes a substrate, a compound semiconductor layer provided on the substrate; and a buffer layer interposed between the compound semiconductor layer and the substrate. The compound semiconductor layer includes a first semiconductor area having a first conductivity type and a second semiconductor area having a second conductivity type. The buffer layer includes a high electron density area. In the buffer layer, an electron density of the high electron density area is higher than an electron density outside the high electron density area.

Abstract: A device for producing electricity. In one embodiment, the device comprises a doped germanium or a doped GaAs substrate and a plurality of stacked material layers (some of which are doped) above the substrate. These stacked material layers, which capture the beta particles and generate electrical current, may include, in various embodiments, GaAs, InAlP, InGaP, InAlGaP, AlGaAs, and other semiconductor materials. A beta particle source generates beta particles that impinge the stack, create electron-hole pairs, and thereby generate electrical current. In another embodiment the device comprises a plurality of epi-liftoff layers and a backing support material.

Abstract: A method for manufacturing a light emitting element includes: a GaN layer is formed on an AlN-deposited plain or patterned substrate, and the stress between different materials is changed and buffered through thermal treatment of annealing under H2 atmosphere or under H2 and NH3 mixed atmosphere, thus eliminating epitaxial wafer warp caused by such stress and improving epitaxial quality and light-emitting efficiency of the light-emitting element.

Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

Abstract: Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained.

Abstract: Provided is a method for fabricating a wafer product including an active layer grown on a gallium oxide substrate and allowing an improvement in emission intensity. In step S105, a buffer layer 13 comprised of a Group III nitride such as GaN, AlGaN, or AlN is grown at 600 Celsius degrees on a primary surface 11a of a gallium oxide substrate 11. After the growth of the buffer layer 13, while supplying a gas G2, which contains hydrogen and nitrogen, into a growth reactor 10, the gallium oxide substrate 11 and the buffer layer 13 are exposed to an atmosphere in the growth reactor 11 at 1050 Celsius degrees. A Group III nitride semiconductor layer 15 is grown on the modified buffer layer. The modified buffer layer includes, for example, voids. The Group III nitride semiconductor layer 15 can be comprised of GaN and AlGaN. When the Group III nitride semiconductor layer 15 is formed of these materials, excellent crystal quality is obtained on the modified buffer layer 14.

Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: The plasma-assisted metal-organic chemical vapor deposition (MOCVD) fabrication of a p-type group III-nitride material is described. For example, a method of fabricating a p-type group III-nitride material includes generating a nitrogen-based plasma. A nitrogen-containing species from the nitrogen-based plasma is reacted with a group III precursor and a p-type dopant precursor in a metal-organic chemical vapor deposition (MOCVD) chamber. A group III-nitride layer including p-type dopants is then formed above a substrate.

Abstract: A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10?3 ohm·cm and a thermal conductivity of greater than 100 W·m?1·K?1, a bonding layer, a first seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, a second seed layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and an active layer of a monocrystalline material of composition AlxInyGa(1-x-y)N, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750° C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 ?, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm·cm2.

Abstract: Methods, semiconductor material stacks and equipment for manufacture of light emitting diodes (LEDs) with improve crystal quality. A growth stopper is deposited between nuclei for a group III-V material, such as GaN, to form a nano mask. The group III-V material is laterally overgrown from a region of the nuclei not covered by the nano mask to form a continuous material layer with reduced dislocation density in preparation for subsequent growth of n-type and p-type layers of the LED. The lateral overgrowth from the nuclei may further recover the surface morphology of the buffer layer despite the presence of the nano mask. Presence of the growth stopper may further result in void formation on a substrate side of an LED stack to improve light extraction efficiency.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Abstract: An object is to provide a method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf). The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor and an active layer formed between the n-type nitride semiconductor and the p-type nitride semiconductor, wherein the n-type nitride semiconductor includes at least an n-type contact layer and an n-side GaN layer, the n-side GaN layer consists of a single or a plurality of undoped and/or n-type layers, and the method includes the step of forming the n-side GaN layer by organic metal vapor deposition with the growth temperature set within the range of 500 to 1000° C., such that the n-side GaN layer is formed between the n-type contact layer and the active layer.

Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.

Abstract: An object is to provide a method of manufacturing a nitride semiconductor light emitting device having high light emission output and allowing decrease in forward voltage (Vf). The invention is directed to a method of manufacturing a nitride semiconductor light emitting device including at least an n-type nitride semiconductor, a p-type nitride semiconductor and an active layer formed between the n-type nitride semiconductor and the p-type nitride semiconductor, wherein the n-type nitride semiconductor includes at least an n-type contact layer and an n-side GaN layer, the n-side GaN layer consists of a single or a plurality of undoped and/or n-type layers, and the method includes the step of forming the n-side GaN layer by organic metal vapor deposition with the growth temperature set within the range of 500 to 1000° C., such that the n-side GaN layer is formed between the n-type contact layer and the active layer.

Abstract: A method of forming a well-anchored carbon nanotube (CNT) array, as well as thermal interfaces that make use of CNT arrays to provide very high thermal contact conductance. A thermal interface is formed between two bodies by depositing a continuous array of carbon nanotubes on a first of the bodies so that, on mating the bodies, the continuous array is between surface portions of the first and second bodies. The thermal interface preferably includes a multilayer anchoring structure that promotes anchoring of the continuous array of carbon nanotubes to the first body. The anchoring structure includes a titanium bond layer contacting the surface portion of the first body, and an outermost layer with nickel or iron catalytic particles from which the continuous array of carbon nanotubes are nucleated and grown. Additional thermal interface materials (TIM's) can be used in combination with the continuous array of carbon nanotubes.

Abstract: A method of producing a semiconductor wafer includes placing a base wafer within a reaction chamber, and epitaxially growing a p-type Group 3-5 compound semiconductor on the base wafer by supplying, into the reaction chamber, a Group 3 source gas consisting of an organometallic compound of a Group 3 element, a Group 5 source gas consisting of a compound of a Group 5 element, and an impurity gas including an impurity that is to be incorporated as a dopant into a semiconductor to serve as a donor. Here, during the epitaxial growth of the p-type Group 3-5 compound semiconductor, the flow rate of the impurity gas and the flow rate ratio of the Group 5 source gas to the Group 3 source gas are set so that the product N×d (cm?2) of the residual carrier concentration N (cm?3) and the thickness d (cm) of the p-type Group 3-5 compound semiconductor may be 8.0×1011 or less.

Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained.

Abstract: A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified.

Abstract: A manufacture method for zinc oxide (ZnO) based semiconductor crystal includes providing a substrate having a Zn polarity plane; and reacting at least zinc (Zn) and oxygen (O) on the Zn polarity plane of said substrate to grow ZnO based semiconductor crystal on the Zn polarity plane of said substrate in a Zn rich condition. (a) An n-type ZnO buffer layer is formed on a Zn polarity plane of a substrate. (b) An n-type ZnO layer is formed on the surface of the n-type ZnO buffer layer. (c) An n-type ZnMgO layer is formed on the surface of the n-type ZnO layer. (d) A ZnO/ZnMgO quantum well layer is formed on the surface of the n-type ZnMgO layer, by alternately laminating a ZnO layer and a ZnMgO layer. @(e) A p-type ZnMgO layer is formed on the surface of the ZnO/ZnMgO quantum well layer. (f) A p-type ZnO layer is formed on the surface of the p-type ZnMgO layer. @(g) An electrode is formed on the n-type ZnO layer and p-type ZnO layer. The n-type ZnO layer is formed under a Zn rich condition at the step (b).

Abstract: A method of forming a nitride film by hydride vapor phase epitaxy, the method including: sequentially disposing at least one group III metal source including impurities and a substrate in an external reaction chamber and an internal reaction chamber sequentially located in the direction of gas supply and heating each of the external reaction chamber and the internal reaction chamber at a growth temperature; forming a metal chloride by supplying hydrogen chloride gas and carrier gas into the external reaction chamber to react with the group III metal source and transferring the metal chloride to the substrate; and forming the nitride film doped with the impurities on the substrate by reacting the transferred metal chloride with nitrogen source gas supplied to the internal reaction chamber.

Abstract: A new structure of a semiconductor optical device and a method to produce the device are disclosed. One embodiment of the optical device of the invention provides a blocking region including, from the side close to the mesa, a p-type first layer and a p-type second layer. The first layer is co-doped with an n-type impurity and a p-type impurity. The doping concentration of the p-type impurity in the first layer is smaller than that in the second layer, so, the first layer performs a function of a buffer layer for the Zn diffusion from the second layer to the active layer in the mesa structure.

Abstract: A manufacturing method of an image sensor of vertical type is provided that includes: forming an insulation layer with a metal wiring and a contact plug therein on a first substrate; bonding a second substrate having an image sensing unit over the insulation layer; forming a trench in the second substrate to divide the image sensing unit for each pixel; forming a PTI by gap-filling the trench with insulating material; forming a first material layer over the PTI, the image sensing unit, and the insulation layer; and forming a second material layer over the first material layer and performing a deuterium annealing process thereon. The crystal defects of the substrate generated when performing the trench etching on the donor substrate to define unit pixels are cured by performing the deuterium annealing process, making it possible to improve the sensitivity and illumination characteristics of the image sensor of vertical type.

Abstract: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the side surfaces of the one or more convex portions of the first nitride semiconductor layer.

Abstract: A method for producing a region of increased doping in an n-doped semiconductor layer which is buried in a semiconductor body of a vertical power transistor and which is arranged between a p-doped body region facing the front side contact of the power transistor and an n-doped substrate facing the rear side contact of the power transistor has the following steps: a) irradiation of at least one part of the surface of the semiconductor body with protons, and b) heat treatment of the semiconductor body.

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.

Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.