Deposition On A Semiconductor Substrate Not Being Group Iii-v Compound (epo) Patents (Class 257/E21.112)
  • Patent number: 10141435
    Abstract: The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 27, 2018
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Daisuke Ueda
  • Patent number: 10134884
    Abstract: The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 20, 2018
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Daisuke Ueda
  • Patent number: 10134883
    Abstract: The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 20, 2018
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Daisuke Ueda
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 9006827
    Abstract: A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: John G. Massey, Scott J. McAllister, Charles J. Montrose, Stewart E. Rauch, III
  • Patent number: 8786017
    Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 22, 2014
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Patent number: 8772873
    Abstract: A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 8, 2014
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Patent number: 8664027
    Abstract: A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Associates, Inc.
    Inventors: San Yu, Atul Gupta
  • Patent number: 8648328
    Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Patent number: 8617945
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 8410523
    Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 2, 2013
    Inventors: Diana L. Huffaker, Larry R. Dawson, Ganesh Balakrishnan
  • Patent number: 8372671
    Abstract: Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Publication number: 20130005118
    Abstract: Methods of forming III-V materials using metal organic chemical vapor deposition (MOCVD) with chlorine cleans operations are described. A chlorine-clean operation may further season an MOCVD process for improved throughput for high volume manufacturing.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 3, 2013
    Inventors: Sung Won Jun, Yan Wang, Hua Chung, Jiang Lu, Kuan Chien Keris Shen, Shiva Rai
  • Publication number: 20120313106
    Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Zhi He
  • Patent number: 8329541
    Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peide Ye, Zhiyuan Cheng, Yi Xuan, Yanqing Wu, Bunmi Adekore, James Fiorenza
  • Patent number: 8212288
    Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Jun Komiyama, Kenichi Eriguchi, Hiroshi Oishi, Yoshihisa Abe, Akira Yoshida, Shunichi Suzuki
  • Publication number: 20120153261
    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.
    Type: Application
    Filed: June 10, 2011
    Publication date: June 21, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Publication number: 20120145990
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Application
    Filed: October 24, 2011
    Publication date: June 14, 2012
    Inventors: Lars SAMUELSON, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8188573
    Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 29, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Suh-Fang Lin, Wei-Hung Kuo
  • Patent number: 8138003
    Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: March 20, 2012
    Assignee: Siltron, Inc.
    Inventors: Doo-Soo Kim, Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee
  • Patent number: 8084337
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: December 27, 2011
    Assignee: QuNano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 7955959
    Abstract: A method for manufacturing GaN-based film LED based on masklessly transferring photonic crystal structure is disclosed. Two dimensional photonic crystals are formed on a sapphire substrate. Lattice quality of GaN-based epitaxy on the sapphire substrate is improved, and the internal quantum efficiency of GaN-based LED epitaxy is increased. After the GaN-based film is transferred onto heat sink substrate, the two dimensional photonic crystals structure is masklessly transferred onto the light exiting surface of the GaN-based film by using different etching rates between the GaN material and the SiO2 mask, so that light extraction efficiency of the GaN-based LED is improved. That is, the GaN-based film LED according to the invention has a relatively high illumination efficiency and heat sink.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: June 7, 2011
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Jyh Chiarng Wu, Xuejiao Lin, Qunfeng Pan, Meng Hsin Yeh, Huijun Huang
  • Patent number: 7951694
    Abstract: A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising AlxInyGa(1?(x+y))As(0?x+y?1) or AlxInyGa(1?(x+y))P(0?x+y?1) on the substrate; in-situ annealing the wetting layer; growing a first AlGaInN layer on the wetting layer using plasma activated nitrogen as the source of nitrogen with an additional flux of phosphorous or arsenic; and growing a second AlGaInN layer on the first AlGaInN layer using ammonia as a source of nitrogen.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jonathan Heffernan
  • Patent number: 7935985
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 3, 2011
    Assignee: The Regents of the University of Califonia
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong
  • Patent number: 7915698
    Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses on the base substrate that become larger from a central portion of the base substrate towards a peripheral portion when growing a nitride semiconductor film. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: March 29, 2011
    Assignee: Siltron, Inc.
    Inventors: Doo-Soo Kim, Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee
  • Patent number: 7880230
    Abstract: The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer. This layer is patterned into line types to constitute active patterns. Moreover, a first insulation layer forms between the active patterns and gates form on the active patterns as well as the first insulation layer to extend perpendicularly to the active patterns. In addition, a source forms in the active pattern on one side of each gate, a drain forms in the active pattern on the other side of each gate which is achieved by filling a metal layer. Continuing, a contact plug forms between the gates on the source and an interlayer dielectric forms on the contact plug in addition to the gates. Finally, a bit line forms on the interlayer dielectric to extend perpendicularly to the gates and come into contact with the drain.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: February 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Sung Lee
  • Patent number: 7868327
    Abstract: A thin film transistor (TFT) and a method of manufacturing the same, and more particularly, a TFT for reducing leakage current and a method of manufacturing the same are provided. The TFT includes a flexible substrate, a diffusion preventing layer formed on the flexible substrate, a buffer layer formed of at least two insulated materials on the diffusion preventing layer, a semiconductor layer formed on a region of the buffer layer to include a channel layer and a source and drain region, a gate insulating layer formed on the buffer layer including the semiconductor layer, a gate electrode formed on the gate insulating layer in a region corresponding to the channel layer, an interlayer insulating layer formed on the gate insulating layer including the gate electrode, and source and drain electrodes formed in the interlayer insulating layer to include a predetermined contact hole that exposes at least a region of the source and drain region and to be connected to the source and drain region.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: January 11, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jae Kyeong Jeong, Hyun Soo Shin, Se Yeoul Kwon, Yeon Gon Mo
  • Patent number: 7812366
    Abstract: An AlGaN composition is provided comprising a group III-Nitride active region layer, for use in an active region of a UV light emitting device, wherein light-generation occurs through radiative recombination of carriers in nanometer scale size, compositionally inhomogeneous regions having band-gap energy less than the surrounding material. Further, a semiconductor UV light emitting device having an active region layer comprised of the AlGaN composition above is provided, as well as a method of producing the AlGaN composition and semiconductor UV light emitting device, involving molecular beam epitaxy.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 12, 2010
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Anand Venktesh Sampath, Charles J. Collins, Gregory Alan Garrett, H. Paul Shen, Michael Wraback
  • Patent number: 7759737
    Abstract: Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 20, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Tae Moon Roh, Jong Dae Kim
  • Patent number: 7727830
    Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Matthew V. Metz, Marko Radosavlievic, Robert S. Chau
  • Patent number: 7700418
    Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 20, 2010
    Assignee: Sony Corporation
    Inventor: Masafumi Kunii
  • Patent number: 7691724
    Abstract: A method for manufacturing an SOI substrate, including the steps of implanting hydrogen ions from a main surface of a single-crystal silicon substrate having an interstitial oxygen concentration which is equal to or below 1×1018 cm?3; performing an activation treatment with respect to the main surface of at least one of a transparent insulative substrate and the silicon substrate; bonding the main surface of the transparent insulative substrate to the main surface of the silicon substrate at a room temperature; performing a heat treatment with respect to the bonded substrate at a temperature falling within the range of 350° C. to 550° C. and having a cooling rate after the heat treatment that is equal to or below 5° C./minute; and mechanically delaminating a silicon thin film from the silicon substrate to form a silicon film on the main surface of the transparent insulative substrate.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: April 6, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Shoji Akiyama
  • Patent number: 7692213
    Abstract: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 6, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lee Wee Teo, Yung Fu Chong, Elgin Kiok Boone Quek, Alain Chan
  • Publication number: 20100068872
    Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.
    Type: Application
    Filed: November 3, 2008
    Publication date: March 18, 2010
    Inventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu
  • Patent number: 7679104
    Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: March 16, 2010
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yoshihiro Sato, Sadahiro Kato, Masayuki Iwami, Hitoshi Sasaki, Shinya Ootomo, Yuki Niiyama
  • Publication number: 20100052016
    Abstract: A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising AlxInyGa(1?(x/y))As(0?x+y?1) or AlxInyGa(1?(x/y))P(0?x+y?1) on the substrate; in-situ annealing the wetting layer; growing a first AlGaInN layer on the wetting layer using plasma activated nitrogen as the source of nitrogen with an additional flux of phosphorous or arsenic; and growing a second AlGaInN layer on the first AlGaInN layer using ammonia as a source of nitrogen.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Inventors: Stewart Edward HOOPER, Jonathan Heffernan
  • Publication number: 20090315018
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Mantu K. Hudait, Peter G. Tolchinsky, Loren A. Chow, Dmitri Loubychev, Joel M. Fastenau, Amy W.K. Liu
  • Patent number: 7544998
    Abstract: A Silicon on Insulator device is disclosed wherein a parasitic channel induced in a thin film portion of the device is prevented from allowing current flow between the source and drain by a Deep N implant directly below the source or drain. The deep N implant prevents a depletion region from being formed, thereby cutting off current flow between the source and the drain that would otherwise occur.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 9, 2009
    Assignee: NXP B.V.
    Inventor: Theodore Letavic
  • Patent number: 7491627
    Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: February 17, 2009
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 7473587
    Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
  • Publication number: 20080308841
    Abstract: A semiconductor substrate (1) of the present invention is made of nitrides of group III metals having wurtzite crystal structure and is grown in vapor phase either on a (0001) oriented foreign substrate (2), lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer (3) of the semiconductor substrate materials and has a highly reduced dislocation density.
    Type: Application
    Filed: May 19, 2005
    Publication date: December 18, 2008
    Inventors: Maxim Odnoblyudov, Vladislav Bougrov, Alexei Romanov, Teemu Lang
  • Publication number: 20080308812
    Abstract: A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more.
    Type: Application
    Filed: August 5, 2005
    Publication date: December 18, 2008
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Kazumasa Kiyomi, Hirobumi Nagaoka, Hirotaka Oota, Isao Fujimura
  • Patent number: 7462913
    Abstract: A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: December 9, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hidetoshi Muramoto, Akira Yamada, Tomohisa Suzuki
  • Publication number: 20080283821
    Abstract: Example embodiments are directed to a method of growing GaN single crystals on a silicon substrate, a method of manufacturing a GaN-based light emitting device using the silicon substrate, and a GaN-based light emitting device. The method of growing the GaN single crystals may include forming a buffer layer including a TiN group material or other like material on a silicon substrate, forming a nano-pattern including silicon oxide on the buffer layer, and growing GaN single crystals on the buffer layer and the nano-pattern.
    Type: Application
    Filed: February 29, 2008
    Publication date: November 20, 2008
    Inventors: Sung-soo Park, June-Key Lee
  • Patent number: 7439135
    Abstract: A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 21, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Publication number: 20080237640
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong
  • Publication number: 20080210951
    Abstract: One embodiment of the present invention provides a semiconductor light-emitting device which includes: (1) a silicon (Si) substrate; (2) a silver (Ag) transition layer which is formed on a surface of the Si substrate, wherein the Ag transition layer covers the Si substrate surface; and (3) an InGaAlN, ZnMgCdO, or ZnBeCdO-based semiconductor light-emitting structure which is fabricated on the Ag-coated Si substrate. Note that the Ag transition layer prevents the Si substrate surface from forming an amorphous overcoat with reactant gases used for growing the semiconductor light-emitting structure.
    Type: Application
    Filed: November 17, 2006
    Publication date: September 4, 2008
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Fengyi Jiang, Bilin Shao, Li Wang, Wenqing Fang
  • Publication number: 20080200013
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 21, 2008
    Applicant: Nitronex Corporation
    Inventors: Edwin Lanier Piner, John Claassen Roberts, Pradeep Rajagopal
  • Publication number: 20080191203
    Abstract: A GaN layer (12) is formed on a planarized surface of a ZnO substrate (11) to provide a nitride semiconductor device (10) having the GaN layer. The GaN layer (12) is formed by a first film-forming step of allowing epitaxial growth of GaN at a temperature not higher than 300° C., and a second film-forming step of allowing epitaxial growth of GaN at a temperature not lower than 550° C. on a film of GaN formed by the first film-forming step.
    Type: Application
    Filed: January 31, 2006
    Publication date: August 14, 2008
    Applicant: KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY
    Inventors: Hiroshi Fujioka, Atsushi Kobayashi
  • Patent number: 7399692
    Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 15, 2008
    Assignee: International Rectifier Corporation
    Inventors: Zhi He, Robert Beach