Deposition On An Insulating Or A Metallic Substrate (epo) Patents (Class 257/E21.113)
-
Patent number: 11862459Abstract: A semiconductor device having a planar III-N semiconductor layer includes a substrate including a wafer and a buffer layer of a buffer material different from a material of the wafer, the buffer layer having a growth surface, an array of nanostructures epitaxially grown from the growth surface, a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T, where the number of lattice cells spanning a center distance between adjacent nanostructures are different at the growth surface and at the coalesced planar layer, and a growth layer epitaxially grown on the planar layer.Type: GrantFiled: June 20, 2022Date of Patent: January 2, 2024Assignee: HEXAGEM ABInventors: Jonas Ohlsson, Lars Samuelson, Kristian Storm, Rafal Ciechonski, Bart Markus
-
Patent number: 11437233Abstract: A base substrate includes a supporting substrate comprising aluminum oxide, and a base crystal layer provided on a main face of the supporting substrate, comprising a crystal of a nitride of a group 13 element and having a crystal growth surface. At lease one of a metal of a group 13 element and a reaction product of a material of the supporting substrate and the crystal of the nitride of the group 13 element is present between the raised part and the supporting substrate. The reaction product contains at least aluminum and a group 13 element.Type: GrantFiled: March 24, 2020Date of Patent: September 6, 2022Assignee: NGK INSULATORS, LTD.Inventors: Masashi Goto, Masahiro Sakai, Shohei Oue, Takashi Yoshino
-
Patent number: 11348785Abstract: An apparatus for manufacturing a group III nitride single crystal including: a reaction vessel including a reaction area, wherein in the reaction area, a group III source gas and a nitrogen source gas are reacted such that a group III nitride crystal is grown on a substrate; a susceptor arranged in the reaction area and supporting the substrate; a group III source gas supply nozzle supplying the group III source gas to the reaction area; and a nitrogen source gas supply nozzle supplying the nitrogen source gas to the reaction area, wherein the nitrogen source gas supply nozzle is configured to supply the nitrogen source gas and at least one halogen-based gas selected from the group consisting of a hydrogen halide gas and a halogen gas to the reaction area.Type: GrantFiled: May 24, 2019Date of Patent: May 31, 2022Assignee: TOKUYAMA CORPORATIONInventors: Toru Nagashima, Masayuki Fukuda
-
Patent number: 9711404Abstract: A semiconductor device includes a substrate that includes a first region and a second region adjacent to the first region. The first region has a thickness that is smaller than a thickness of the second region, and a nitride semiconductor layer is provided on the first region of the substrate.Type: GrantFiled: August 28, 2015Date of Patent: July 18, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi Shibata
-
Patent number: 9647175Abstract: The present disclosure provides a light emitting element, wherein each of first and second semiconductor layers has first and second pits disposed therein, wherein the first pit has a first depth and the second pit has a second depth smaller than the first depth, and the first and second pits are coupled to each other, wherein a density of the second pits in an upper portion of the second semiconductor layer is lower than a density of the second pits in an upper portion of the first semiconductor layer, wherein a density of the first pits in the upper portion of the second semiconductor layer is equal to a density of the first pits in the upper portion of the first semiconductor layer.Type: GrantFiled: October 6, 2014Date of Patent: May 9, 2017Assignee: LG INNOTEK CO., LTD.Inventor: Jong Pil Jeong
-
Patent number: 9287453Abstract: In the case that a functional layer, made of a nitride of a group 13 element, is formed on a composite substrate including a sapphire body and a gallium nitride crystal layer disposed over the sapphire body, the deviation of the function is prevented. The composite substrate 4 includes a sapphire body 1A and a gallium nitride crystal layer 3 disposed over the sapphire body. Aa warpage of the composite substrate is in a range of not less than +40 ?m and not more than +80 ?m per 5.08 cm in length.Type: GrantFiled: September 14, 2015Date of Patent: March 15, 2016Assignee: NGK INSULATORS, LTD.Inventors: Makoto Iwai, Katsuhiro Imai, Masahiro Sakai
-
Patent number: 9023673Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.Type: GrantFiled: June 13, 2013Date of Patent: May 5, 2015Assignee: Ostendo Technologies, Inc.Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
-
Patent number: 9018093Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.Type: GrantFiled: January 25, 2013Date of Patent: April 28, 2015Assignee: ASM IP Holding B.V.Inventors: Naoto Tsuji, Fumitaka Shoji
-
Patent number: 8871546Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.Type: GrantFiled: January 21, 2014Date of Patent: October 28, 2014Assignee: Opto Tech CorporationInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
-
Method and system for laser separation for exclusion region of multi-junction photovoltaic materials
Patent number: 8772078Abstract: A method for laser separation of a thin film structure with multi junction photovoltaic materials. The method includes providing an optically transparent substrate having a thickness, a back surface region, and a front surface region including an edge region. The method further includes forming a thin film structure including a conductive layer on the optical transparent substrate. The conductive layer immediately overlies the front surface region. Additionally, the method includes aligning a laser beam with a beam spot on a first portion of the edge region from the back surface region through the thickness of the optically transparent substrate. The method further includes subjecting at least partially the conductive layer overlying the first portion via absorbed energy from the laser beam to separate an edge portion of the thin film structure from the first portion of the edge region.Type: GrantFiled: February 19, 2009Date of Patent: July 8, 2014Assignee: Stion CorporationInventor: Chester A. Farris, III -
Patent number: 8623747Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes forming an aluminum oxide coating on the surface of the silicon substrate, the aluminum oxide being substantially crystal lattice matched to the surface of the silicon substrate and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide coating substantially crystal lattice matched to the surface of the aluminum nitride.Type: GrantFiled: December 17, 2012Date of Patent: January 7, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark
-
Patent number: 8524012Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.Type: GrantFiled: January 24, 2012Date of Patent: September 3, 2013Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
-
Patent number: 8507304Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.Type: GrantFiled: July 15, 2010Date of Patent: August 13, 2013Assignee: Applied Materials, Inc.Inventors: Olga Kryliouk, Yuriy Melnik, Hidehiro Kojiri, Tetsuya Ishikawa
-
Patent number: 8409892Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.Type: GrantFiled: April 14, 2011Date of Patent: April 2, 2013Assignee: Opto Tech CorporationInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
-
Patent number: 8357594Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.Type: GrantFiled: February 22, 2011Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-soo Park, Moon-sang Lee
-
Publication number: 20120264246Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: OPTO TECH CORPORATIONInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
-
Publication number: 20120223329Abstract: Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method.Type: ApplicationFiled: November 9, 2010Publication date: September 6, 2012Applicant: TOKUYAMA CORPORATIONInventors: Toru Kinoshita, Kazuya Takada
-
Patent number: 8193079Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.Type: GrantFiled: February 9, 2007Date of Patent: June 5, 2012Assignee: The Regents of the University of CaliforniaInventors: John F. Kaeding, Hitoshi Sato, Michael Iza, Hirokuni Asamizu, Hong Zhong, Steven P. DenBaars, Shuji Nakamura
-
Publication number: 20120119222Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
-
Patent number: 8128756Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13 } gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.Type: GrantFiled: February 1, 2010Date of Patent: March 6, 2012Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
-
Patent number: 8110482Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.Type: GrantFiled: February 22, 2010Date of Patent: February 7, 2012Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: John F. Kaeding, Dong-Seon Lee, Michael Iza, Troy J. Baker, Hitoshi Sato, Benjamin A. Haskell, James S. Speck, Steven P. DenBaars, Shuji Nakamura
-
Patent number: 8110484Abstract: A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 ?m and arranged at a spacing of 250 to 10,000 ?m; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 ?cm?r?0.01 ?cm, a thickness of 100 ?m or more, and a radius of bow curvature U of 3.5 m?U?8 m.Type: GrantFiled: November 19, 2010Date of Patent: February 7, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka Sato, Seiji Nakahata, Makoto Kiyama
-
Publication number: 20110204377Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.Type: ApplicationFiled: February 22, 2011Publication date: August 25, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-soo Park, Moon-sang Lee
-
Patent number: 7977673Abstract: To provide a semiconductor layer in which a GaN system epitaxial layer having high crystal quality can be obtained. The semiconductor layer includes a ?-Ga2O3 substrate 1 made of a ?-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the ?-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD method. Since lattice constants of the GaN layer 2 and the GaN growth layer 3 match each other, and the GaN growth layer 3 grows so as to succeed to high crystalline of the GaN layer 2, the GaN growth layer 3 having high crystalline is obtained.Type: GrantFiled: August 4, 2004Date of Patent: July 12, 2011Assignee: Koha Co., Ltd.Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
-
Patent number: 7923736Abstract: A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.Type: GrantFiled: April 13, 2010Date of Patent: April 12, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventor: Keun-Soo Lee
-
Patent number: 7812366Abstract: An AlGaN composition is provided comprising a group III-Nitride active region layer, for use in an active region of a UV light emitting device, wherein light-generation occurs through radiative recombination of carriers in nanometer scale size, compositionally inhomogeneous regions having band-gap energy less than the surrounding material. Further, a semiconductor UV light emitting device having an active region layer comprised of the AlGaN composition above is provided, as well as a method of producing the AlGaN composition and semiconductor UV light emitting device, involving molecular beam epitaxy.Type: GrantFiled: March 15, 2006Date of Patent: October 12, 2010Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Anand Venktesh Sampath, Charles J. Collins, Gregory Alan Garrett, H. Paul Shen, Michael Wraback
-
Patent number: 7811847Abstract: Because of a large lattice mismatch between a sapphire substrate and a group III-V compound semiconductor, a good crystal is difficult to grow. A high-quality AlN buffer growth structure A on a sapphire substrate includes a sapphire (0001) substrate 1, an AlN nucleation layer 3 formed on the sapphire substrate 1, a pulsed supplied AlN layer 5 formed on the AlN nucleation layer 3, and a continuous growth AlN layer 7 formed on the pulsed supplied AlN layer 5. Formed on the continuous growth AlN layer 7 is at least one set of a pulsed supplied AlN layer 11 and a continuous growth AlN layer 15. The AlN layer 3 is grown in an initial nucleation mode which is a first growth mode by using an NH3 pulsed supply method. The pulsed supplied AlN layer 5 is formed by using NH3 pulsed supply in a low growth mode which is a second growth mode that increases a grain size and reduces dislocations and therefore is capable of reducing dislocations and burying the nucleation layer 3.Type: GrantFiled: March 26, 2008Date of Patent: October 12, 2010Assignee: RikenInventors: Hideki Hirayama, Tomoaki Ohashi, Norihiko Kamata
-
Patent number: 7800116Abstract: A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening.Type: GrantFiled: March 28, 2008Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Tomohiro Murata, Masayuki Kuroda, Tetsuzo Ueda
-
Patent number: 7785991Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.Type: GrantFiled: November 16, 2007Date of Patent: August 31, 2010Assignee: STMicroelectronics SAInventors: Sylvain Joblot, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz
-
Patent number: 7704331Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.Type: GrantFiled: January 9, 2007Date of Patent: April 27, 2010Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
-
Patent number: 7691658Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1?xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1?xN nucleation layer, and cooling the substrate under a nitrogen overpressure.Type: GrantFiled: January 19, 2007Date of Patent: April 6, 2010Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: John F. Kaeding, Dong-Seon Lee, Michael Iza, Troy J. Baker, Hitoshi Sato, Benjamin A. Haskell, James S. Speck, Steven P. DenBaars, Shuji Nakamura
-
Patent number: 7687293Abstract: A method for enhancing growth of device-quality planar semipolar nitride semiconductor thin films via metalorganic chemical vapor deposition (MOCVD) by using an (Al,In,Ga)N nucleation layer containing at least some indium. Specifically, the method comprises loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.Type: GrantFiled: January 19, 2007Date of Patent: March 30, 2010Assignee: The Regents of the University of CaliforniaInventors: Hiroshi Sato, John F. Kaeding, Michael Iza, Troy J. Baker, Benjamin A. Haskell, Steven P. DenBaars, Shuji Nakamura
-
Publication number: 20090302336Abstract: Semiconductor wafers, semiconductor devices, and methods of making semiconductor wafers and devices are provided. Embodiments of the present invention are especially suitable for use with substrate substitution applications, such in the case of fabricating vertical LED. One embodiment of the present invention includes a method of making a semiconductor device, the method comprising providing a substrate; forming a plurality of polishing stops on the substrate; growing one or more buffer layers on the substrate; growing one or more epitaxial layers on the one or more buffer layers; and applying one or more metal layers to the one or more epitaxial layers. Additionally, the steps of affixing a second substrate to the one or more metal layers and removing the base substrate using a mechanical thinning process may be performed.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Applicant: Hong Kong Applied Science and Technology Research InstituteInventor: Shu YUAN
-
Publication number: 20090155947Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.Type: ApplicationFiled: October 7, 2008Publication date: June 18, 2009Inventors: Ho Sun Paek, Jeong Wook Lee, Youn Joon Sung
-
Publication number: 20090128991Abstract: Capacitive circuits and methods of forming capacitive circuits including a first capacitor and a second capacitor connected in parallel to the first capacitor, wherein the first capacitor is positioned at least partially above the second capacitor.Type: ApplicationFiled: November 21, 2007Publication date: May 21, 2009Inventor: Richard A. Mauritzson
-
Publication number: 20090108297Abstract: A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 ?m to 100 ?m are arranged at an interval Dw from 250 ?m to 2000 ?m, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R5/3 is set to 1 to 10 and a gas containing iron, and removing the underlying substrate, to thereby obtain a free-standing semi-insulating nitride semiconductor substrate having a specific resistance not smaller than 1×105 ?cm and a thickness not smaller than 100 ?m. Thus, the semi-insulating nitride semiconductor crystal substrate in which warpage is less and cracking is less likely can be obtained.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka SATO, Seiji NAKAHATA, Makoto KIYAMA
-
Publication number: 20090090917Abstract: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm?2. A GaN single crystal production method includes introducing group III and V raw material gases on a substrate, and growing a GaN single crystal on the substrate. The growth temperature is within the range of not less than 1100° C. and not more than 1400° C., the group V to III raw material gas partial pressure ratio (V/III ratio) is within the range of not less than 0.4 and not more than 1, and the number density of polarity inversion zones in a surface of the substrate is not more than 20 cm?2.Type: ApplicationFiled: January 30, 2008Publication date: April 9, 2009Applicant: HITACHI CABLE, LTD.Inventors: Yuichi Oshima, Masatomo Shibata
-
Patent number: 7514306Abstract: A method for manufacturing a semiconductor device, includes: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof; and c) adding the metal element to at least a vicinity of a surface of the amorphous semiconductor film to enhance re-crystallization of a semiconductor.Type: GrantFiled: March 7, 2007Date of Patent: April 7, 2009Assignee: Seiko Epson CorporationInventor: Sumio Utsunomiya
-
Patent number: 7504274Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.Type: GrantFiled: January 9, 2007Date of Patent: March 17, 2009Assignees: The Regents of the University of California, The Japan Science and Technology AgencyInventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
-
Publication number: 20090065786Abstract: A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a relevant device using nitride thin film. There is provided a method for growing a nitride thin film on a sapphire substrate, comprising irradiating a sapphire substrate having undergone high temperature hydrogen treatment with electron beams and depositing a nitride thin film on the substrate having undergone the electron beam irradiation by using the metal-organic chemical vapor deposition technique to thereby accomplish patterning of nitride thin film.Type: ApplicationFiled: March 14, 2006Publication date: March 12, 2009Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, National University Corporation Shizuoka Univ.Inventors: Masatomo Sumiya, Shunro Fuke
-
Publication number: 20090057646Abstract: Because of a large lattice mismatch between a sapphire substrate and a group III-V compound semiconductor, a good crystal is difficult to grow. A high-quality AlN buffer growth structure A on a sapphire substrate includes a sapphire (0001) substrate 1, an AlN nucleation layer 3 formed on the sapphire substrate 1, a pulsed supplied AlN layer 5 formed on the AlN nucleation layer 3, and a continuous growth AlN layer 7 formed on the pulsed supplied AlN layer 5. Formed on the continuous growth AlN layer 7 is at least one set of a pulsed supplied AlN layer 11 and a continuous growth AlN layer 15. The AlN layer 3 is grown in an initial nucleation mode which is a first growth mode by using an NH3 pulsed supply method. The pulsed supplied AlN layer 5 is formed by using NH3 pulsed supply in a low growth mode which is a second growth mode that increases a grain size and reduces dislocations and therefore is capable of reducing dislocations and burying the nucleation layer 3.Type: ApplicationFiled: March 26, 2008Publication date: March 5, 2009Applicant: RIKENInventors: Hideki Hirayama, Tomoaki Ohashi, Norihiko Kamata
-
Publication number: 20080283823Abstract: A gallium-nitride-based semiconductor stacked structure includes a sapphire substrate; a low temperature-deposited buffer layer which is composed of a Group III nitride material of AlxGayN (0.5<Y?1, X+Y=1) containing gallium (Ga) in a predominant amount with respect to aluminum (Al), which has been grown at low temperature and which is provided in a junction area thereof joined to a (0001) plane (c-plane) of the sapphire substrate with a single crystal in an as-grown state; and a gallium-nitride (GaN)-based semiconductor layer formed on the low-temperature-deposited buffer layer. The low-temperature-deposited buffer layer is predominantly composed of an as-grown single crystal which has a [1.0.-1.0.] orientation parallel to a [2.-1.1.0.] direction of a lattice forming a (0001) basal plane of the sapphire substrate.Type: ApplicationFiled: June 9, 2005Publication date: November 20, 2008Applicant: SHOWA DENKO K.K.Inventor: Takashi Udagawa
-
Publication number: 20080217625Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0001) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (11-20) plane or (1-100) plane.Type: ApplicationFiled: March 4, 2008Publication date: September 11, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masayuki KURODA, Tetsuzo UEDA
-
Patent number: 7399692Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.Type: GrantFiled: September 29, 2006Date of Patent: July 15, 2008Assignee: International Rectifier CorporationInventors: Zhi He, Robert Beach
-
Publication number: 20080153267Abstract: The invention relates to a method for manufacturing an SOI substrate, associating silicon based areas and areas of GaAs based material at the thin layer of the SOI substrate, the SOI substrate comprising a silicon support supporting successively a layer of dielectric material and a thin layer of silicon.Type: ApplicationFiled: December 19, 2007Publication date: June 26, 2008Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Laurent CLAVELIER, Chrystel DEGUET
-
Publication number: 20080105881Abstract: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.Type: ApplicationFiled: November 2, 2007Publication date: May 8, 2008Inventors: Yong-Jin Kim, Doo-Soo Kim, Ho-Jun Lee, Dong-Kun Lee
-
Patent number: 7276732Abstract: A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.Type: GrantFiled: September 23, 2005Date of Patent: October 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Je Hun Lee, Yang Ho Bae, Beom Seok Cho, Chang Oh Jeong
-
Patent number: 7220324Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.Type: GrantFiled: March 10, 2006Date of Patent: May 22, 2007Assignee: The Regents of the University of CaliforniaInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
-
Patent number: 7186302Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.Type: GrantFiled: May 6, 2005Date of Patent: March 6, 2007Assignees: The Regents of the University of California, The Agency of Industrial Science and TechnologyInventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James Stephen Speck, Steven P. Denbaars, Shuji Nakamura, Umesh Kumar Mishra
-
Patent number: 7109530Abstract: A nitride-based semiconductor element having excellent element characteristics is obtained by fabricating a nitride-based semiconductor layer having excellent crystallinity without performing extended etching. The nitride-based semiconductor element comprises a mask layer, having a recess portion, formed on a substantially flat upper surface of an underlayer to partially expose the upper surface of the underlayer, a nitride-based semiconductor layer formed on the exposed part of the underlayer and the mask layer while forming a void on the recess portion of the mask layer, and a nitride-based semiconductor element layer, formed on the nitride-based semiconductor layer, having an element region. During laterally growth, strain is relaxed thereby improving crystallinity. The underlayer is formed in a substantially flat shape, thereby avoiding extended etching.Type: GrantFiled: March 10, 2004Date of Patent: September 19, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuhiko Hayashi, Tatsuya Kunisato, Hiroki Ohbo, Tsutomu Yamaguchi