Deposition On A Semiconductor Substrate Not Being An Group Iii-v Compound (epo) Patents (Class 257/E21.118)
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Patent number: 8823025Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.Type: GrantFiled: February 20, 2013Date of Patent: September 2, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
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Patent number: 8647904Abstract: Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%.Type: GrantFiled: February 23, 2011Date of Patent: February 11, 2014Assignee: Sharp Kabushiki KaishaInventors: Masahiro Araki, Takaaki Utsumi, Masahiko Sakata
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Patent number: 8609517Abstract: A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).Type: GrantFiled: June 11, 2010Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
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Patent number: 8283661Abstract: Provided is an organic EL display manufacturing method which has: a step wherein an organic EL panel having a substrate and organic EL elements arranged in matrix on the substrate is prepared, and each organic EL element is permitted to have a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a transparent counter electrode disposed on the organic layer, a sealing layer disposed on the transparent counter electrode, and a color filter disposed on the sealing layer; a step of detecting a defective portion on the organic layer in the organic EL element; and a step of breaking the transparent counter electrode in a region on the defective portion of the transparent counter electrode by irradiating the region on the defective portion with a laser beam. The laser beam is radiated by being tilted with respect to the normal line on the display surface of the organic EL panel.Type: GrantFiled: April 20, 2010Date of Patent: October 9, 2012Assignee: Panasonic CorporationInventors: Kazutoshi Miyazawa, Akihisa Nakahashi
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Patent number: 8188573Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.Type: GrantFiled: September 14, 2009Date of Patent: May 29, 2012Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Suh-Fang Lin, Wei-Hung Kuo
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Patent number: 8183134Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.Type: GrantFiled: January 19, 2011Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 8148241Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.Type: GrantFiled: July 23, 2010Date of Patent: April 3, 2012Assignee: Applied Materials, Inc.Inventors: Jie Su, Olga Kryliouk
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Patent number: 7928448Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.Type: GrantFiled: December 4, 2007Date of Patent: April 19, 2011Inventors: Jonathan J. Wierer, Jr., John E. Epler
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Patent number: 7553774Abstract: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure are formed on a primary surface of a first group III-V semiconductor region. After forming the insulating structures, a second group III-V semiconductor region is grown on the first group III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second group III-V semiconductor region. After forming the second group III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to an electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.Type: GrantFiled: February 7, 2008Date of Patent: June 30, 2009Assignee: Sumitomo Electric Industries Ltd.Inventor: Toshio Nomaguchi
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Patent number: 7282381Abstract: The invention relates to a method for the production of self-supporting substrates comprising element III nitrides. More specifically, the invention relates to a method of producing a self-supporting substrate comprising a III-nitride, in particular, gallium nitride (GaN), which is obtained by means of epitaxy using a starting substrate. The invention is characterised in that it consists in depositing a single-crystal silicon-based intermediary layer by way of a sacrificial layer which is intended to be spontaneously vaporised during the III-nitride epitaxy step. The inventive method can be used, for example, to produce a flat, self-supporting III-nitride layer having a diameter greater than 2?.Type: GrantFiled: September 24, 2004Date of Patent: October 16, 2007Assignee: Centre National de la Recherche Scientifique (CNRS)Inventors: Eric Pascal Feltin, Zahia Bougrioua, Gilles Nataf
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Patent number: 7250360Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.Type: GrantFiled: March 2, 2005Date of Patent: July 31, 2007Assignee: Cornell Research Foundation, Inc.Inventors: James R. Shealy, Joseph A. Smart