Abstract: Among others, the present invention provides devices each including a micro-filter, a shutter, a cell counter, a selector, a micro-surgical kit, a timer, and a data processing circuitry, wherein the micro-filter is capable of detecting or filtering circulating tumor cells.

Abstract: A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>.

Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.

Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.

Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.

Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.

Abstract: During the growth of a nitride semiconductor crystal on a nonpolar face nitride substrate, such as an m-face, the gas that constitutes the main flow in the process of heating up to a relatively high temperature range, before growth of the nitride semiconductor layer, (the atmosphere to which the main nitride face of the substrate is exposed) and the gas that constitutes the main flow until growth of first and second nitride semiconductor layers is completed (the atmosphere to which the main nitride face of the substrate is exposed) are primarily those that will not have an etching effect on the nitride, while no Si source is supplied at the beginning of growth of the nitride semiconductor layer. Therefore, nitrogen atoms are not desorbed from near the nitride surface of the epitaxial substrate, thus suppressing the introduction of defects into the epitaxial film. This also makes epitaxial growth possible with a surface morphology of excellent flatness.

Abstract: Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%.

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.

Abstract: Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer.

Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.

Abstract: There is provided a group III nitride semiconductor epitaxial substrate which has a suppressed level of threading dislocation in the vertical direction and excellent crystal quality, the group III nitride semiconductor epitaxial substrate including a substrate (1) for growing an epitaxial film; and an ELO layer (4) having a composition of AlxGa1-xN (0?x?1) formed either on top of the substrate (1) or on top of a group III nitride layer (2) formed on top of the substrate (1), wherein the ELO layer (4) is a layer formed by using a mask pattern (3), which is composed of carbon and is formed either on top of the substrate (1) or on top of the group III nitride layer (2).

Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.

Abstract: A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure.

Abstract: A method of producing a Group-III nitride crystal by coating at least one surface of the seed with a thin wetting layer or film comprised of one or more Group-III and alkali metals.

Abstract: A semiconductor light-emitting element includes a first semiconductor layer having a first conduction type, a second semiconductor layer having a second conduction type, an active layer provided between the first and second semiconductor layers, a polarity inversion layer provided on the second semiconductor layer, and a third semiconductor layer having the second conduction type provided on the polarity inversion layer. Crystal orientations of the first through third semiconductor layers are inverted, with the polarity inversion layer serving as a boundary. The first and third semiconductor layers have uppermost surfaces made from polar faces having common constitutional elements. Hexagonal conical protrusions arising from a crystal structure are formed at outermost surfaces of the first and third semiconductor layers. The first through third semiconductor layers are made from a wurtzite-structure group III nitride semiconductor, and are layered along a C-axis direction of the crystal structure.

Abstract: A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.

Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

Abstract: Provided is an organic EL display manufacturing method which has: a step wherein an organic EL panel having a substrate and organic EL elements arranged in matrix on the substrate is prepared, and each organic EL element is permitted to have a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a transparent counter electrode disposed on the organic layer, a sealing layer disposed on the transparent counter electrode, and a color filter disposed on the sealing layer; a step of detecting a defective portion on the organic layer in the organic EL element; and a step of breaking the transparent counter electrode in a region on the defective portion of the transparent counter electrode by irradiating the region on the defective portion with a laser beam. The laser beam is radiated by being tilted with respect to the normal line on the display surface of the organic EL panel.

Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).

Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.

Abstract: Regarding a base substrate, a plurality of steps are formed stepwise on the principal surface (c-face). Each step has a height difference of 10 to 40 ?m, and an edge is formed parallel to an a-face of a hexagonal crystal of GaN. Meanwhile, the terrace width of each step is set at a predetermined width. The predetermined width is set in such a way that after a GaN crystal is grown on the principal surface of the base substrate, the principal surface is covered up with grain boundaries when the grown GaN crystal is observed from the surface side. The plurality of steps can be formed through, for example, dry etching, sand blasting, lasing, and dicing.

Abstract: Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: the fabrication temperature, annealing temperature and annealing time, is controlled for controlling defect formation in the semiconductor so as to achieve predetermined performance characteristics of the semiconductor.

Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.

Abstract: A semiconductor light emitting device, includes: a substrate including a first major surface and a second major surface, the first major surface including a recess and a protrusion, the second major surface being formed on a side opposite to the first major surface; a first electrode provided on the first major surface; a semiconductor light emitting element provided on the first electrode and electrically connected to the first electrode; a second electrode provided on the second major surface; and a through-electrode provided to pass through the substrate at the recess and electrically connect the first electrode and the second electrode.

Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.

Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.

Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.

Abstract: In one embodiment a method for fabricating a compound nitride semiconductor device comprising positioning one or more substrates on a susceptor in a processing region of a metal organic chemical vapor deposition (MOCVD) chamber comprising a showerhead, depositing a gallium nitride layer over the substrate with a thermal chemical-vapor-deposition process within the MOCVD chamber by flowing a first gallium containing precursor and a first nitrogen containing precursor through the showerhead into the MOCVD chamber, removing the one or more substrates from the MOCVD chamber without exposing the one or more substrates to atmosphere, flowing a chlorine gas into the processing chamber to remove contaminants from the showerhead, transferring the one or more substrates into the MOCVD chamber after removing contaminants from the showerhead, and depositing an InGaN layer over the GaN layer with a thermal chemical-vapor-deposition process within the MOCVD chamber is provided.

Abstract: A method of manufacturing semiconductor light emitting elements with improved yield and emission power uses laser lift-off and comprises the steps of forming a semiconductor grown layer formed of a first semiconductor layer, an active layer, and a second semiconductor layer on a first principal surface of a growth substrate; forming a plurality of junction electrodes apart on the second semiconductor layer and forming guide grooves arranged in a lattice to surround each of the junction electrodes in the second semiconductor layer; joining together a support and the semiconductor grown layer via the junction electrodes; projecting a laser to separate the growth substrate; dividing the semiconductor grown layer into respective element regions for the semiconductor light emitting elements; and cutting the support, thereby separating into the semiconductor light emitting elements.

Abstract: A method of manufacturing epitaxial material used for GaN based LED with low polarization effect, which includes steps of growing n-type InGaAlN layer composed of GaN buffer layer (2) and n-type GaN layer (3), low polarizing active layer composed of InGaAlN multi-quantum well structure polarized regulating and controlling layer (4) and InGaAlN multi-quantum well structure light emitting layer (5) and p-type InGaAlN layer (6) on sapphire or SiC substrate (1) in turn. The method adds InGaAlN multi-quantum well structure polarized regulating and controlling layer, thus reduces polarization effect of quantum well active region.

Abstract: Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.

Abstract: Provided is a Group III nitride-based compound semiconductor light-emitting device including aluminum regions. The Group III nitride-based compound semiconductor light-emitting device includes a sapphire substrate; aluminum regions which are formed on the substrate; an AlN buffer layer; an Si-doped GaN n-contact layer; an n-cladding layer formed of multiple layer units, each including an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer; an MQW light-emitting layer including alternately stacked eight well layers formed of In0.2Ga0.8N and eight barrier layers formed of GaN and Al0.06Ga0.94N; a p-cladding layer formed of multiple layers including a p-type Al0.3Ga0.7N layer and a p-type In0.08Ga0.92N layer; a p-contact layer having a layered structure including two p-type GaN layers having different magnesium concentrations; and an ITO light-transmitting electrode.

Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.

Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.

Abstract: Affords III-nitride crystals having a major surface whose variance in crystallographic plane orientation with respect to an {hkil} plane chosen exclusive of the {0001} form is minimal. A method of manufacturing the III-nitride crystal is one of: conditioning a plurality of crystal plates (10) in which the deviation in crystallographic plane orientation in any given point on the major face (10m) of the crystal plates (10), with respect to an {hkil} plane chosen exclusive of the {0001} form, is not greater than 0.5°; arranging the plurality of crystal plates (10) in a manner such that the plane-orientation deviation, with respect to the {hkil} plane, in any given point on the major-face (10m) collective surface (10a) of the plurality of crystal plates (10) will be not greater than 0.5°, and such that at least a portion of the major face (10m) of the crystal plates (10) is exposed; and growing second III-nitride crystal (20) onto the exposed areas of the major faces (10m) of the plurality of crystal plates (10).

Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.

Abstract: A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 ?m. The substrate satisfies that a ratio of ??/? is not more than 0.1, where ? is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and ?? is a difference (???L) between the thermal expansion coefficient ? and a thermal expansion coefficient ?L calculated from a temperature change in lattice constant of the substrate.

Abstract: A method may produce a resonant cavity light emitting device. A seed gallium nitride crystal and a source material in a nitrogen-containing superheated fluid may provide a medium for mass transport of gallium nitride precursors therebetween. A seed crystal surface may be prepared by applying a first thermal profile between the seed gallium nitride crystal and the source material. Gallium nitride material may be grown on the prepared surface of the seed gallium nitride crystal by applying a second thermal profile between the seed gallium nitride crystal and the source material while the seed gallium nitride crystal and the source material are in the nitrogen-containing superheated fluid. A stack of group III-nitride layers may be deposited on the single-crystal gallium nitride substrate. The stack may include a first mirror sub-stack and an active region adaptable for fabrication into one or more resonant cavity light emitting devices.

Abstract: The present invention discloses a method for fabricating a light emitting diode element, which incorporates an epitaxial process with an etching process to etch LED epitaxial layers bottom up and form side-protrudent structures, whereby the LED epitaxial layers have non-rectangular inclines, which can solve the problem of total reflection and promote light-extraction efficiency. Further, the method of the present invention has a simple fabrication process, which can benefit mass production and lower cost.

Abstract: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure are formed on a primary surface of a first group III-V semiconductor region. After forming the insulating structures, a second group III-V semiconductor region is grown on the first group III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second group III-V semiconductor region. After forming the second group III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to an electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.

Abstract: An object of the present invention is to provide a method of producing a Group III nitride semiconductor device having a chip form which is pentagonal or more highly polygonal maintaining good area efficiency and at a low cost. The inventive method of producing a Group III nitride semiconductor device having a chip shape which is a pentagonal or more highly polygonal shape comprises a first step of epitaxially growing a Group III nitride semiconductor on a substrate to form a semiconductor wafer; a second step of irradiating said semiconductor wafer with a laser beam to form separation grooves; a third step of grinding and/or polishing the main surface side differently from the epitaxially grown main surface of the substrate; and a fourth step of division into individual chips by applying stress to said separation grooves.

Abstract: A method of fabricating a thick gallium nitride (GaN) layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCI and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of forming the porous GaN layer and the thick GaN layer in-situ proceeds in a single chamber. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN etching and growth are performed using an HVPE process gas such that costs are greatly reduced.