Substrate Is Crystalline Insulating Material, E.g., Sapphire (epo) Patents (Class 257/E21.121)
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Patent number: 8384111Abstract: In a semiconductor device fabricated by growing a compound semiconductor layer on a sapphire substrate, a sapphire substrate enabling the semiconductor device to have a high light-extraction efficiency is provided. A plurality of projections 2, 2, . . . are provided at random on a surface of a sapphire substrate 1, and a GaN layer 10 is grown on this surface. Then, a multi-quantum well layer 12, a p-AlGaN layer 14, a p-GaN layer 16, and an ITO layer 18 are formed on the GaN layer 10, and two electrodes 21 and 22 are also formed. In this manner, a semiconductor light-emitting device is fabricated.Type: GrantFiled: February 9, 2010Date of Patent: February 26, 2013Assignee: Yamaguchi UniversityInventors: Kazuyuki Tadatomo, Narihito Okada
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Publication number: 20130023090Abstract: The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate 5 comprising a fiber 1 with a polygonal cross section, and a semiconductor thin film 3 crystallized after film formation on at least one surface of the fiber 1, and a plurality of grooves 8 that extend in a linear direction of the fiber 1 and are arranged at intervals in a width direction are formed on a surface of the fiber 1.Type: ApplicationFiled: September 13, 2012Publication date: January 24, 2013Applicant: THE FURUKAWA ELECTRIC CO., LTD.Inventors: Takashi FUYUKI, Kenkichi Suzuki, Sadayuki Toda, Hisashi Koaizawa
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Patent number: 8338317Abstract: According to various embodiments, a method for processing a semiconductor wafer or die is provided including supplying particles to a plasma such that the particles are activated by the plasma and spraying the activated particles on the semiconductor wafer or die to generate a particle layer on the semiconductor wafer or die.Type: GrantFiled: April 6, 2011Date of Patent: December 25, 2012Assignee: Infineon Technologies AGInventors: Manfred Engelhardt, Hans-Joerg Timme, Ivan Nikitn, Manfred Frank, Thomas Kunstmann, Werner Robl, Guenther Ruhl
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Patent number: 8298840Abstract: Thin freestanding nitride films are used as a growth substrate to enhance the optical, electrical, mechanical and mobility of nitride based devices and to enable the use of thick transparent conductive oxides. Optoelectronic devices such as LEDs, laser diodes, solar cells, biomedical devices, thermoelectrics, and other optoelectronic devices may be fabricated on the freestanding nitride films. The refractive index of the freestanding nitride films can be controlled via alloy composition. Light guiding or light extraction optical elements may be formed based on freestanding nitride films with or without layers. Dual sided processing is enabled by use of these freestanding nitride films. This enables more efficient output for light emitting devices and more efficient energy conversion for solar cells.Type: GrantFiled: May 6, 2011Date of Patent: October 30, 2012Assignee: Goldeneye, Inc.Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
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Patent number: 8288260Abstract: A process for fabricating a semiconductor device. The process includes (a) growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer, (b) growing a barrier layer on the re-channel layer, (c) epitaxially growing a first etch-stop layer on the barrier layer, (d) growing a first contact layer of wide band-gap material on the first etch-stop layer, (e) epitaxially growing a second etch-stop layer on the first contact layer, (f) growing a second contact layer on the second etch-stop layer, where the second contact layer is a highly doped material, and (g) selectively etching portions of the first contact layer, the second etch-stop layer, and the second contact layer to form a gate region.Type: GrantFiled: June 30, 2011Date of Patent: October 16, 2012Assignee: M/A-COM Technology Solutions Holdings, Inc.Inventor: Allen W. Hanson
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Patent number: 8236671Abstract: A method of manufacturing a semiconductor device including a nitride semiconductor layer having high-precision thickness is provided. The method includes steps of: forming a gallium nitride (GaN) layer whose main face is a +c face on a substrate; forming a trench by selectively etching down a partial region in the +c face of the GaN layer; forming a metal layer so as to bury the trench; and separating the substrate and the GaN layer, after that, polishing a ?c face of the GaN layer until the metal layer is exposed, and removing a part in a thickness direction of the GaN layer.Type: GrantFiled: March 22, 2011Date of Patent: August 7, 2012Assignee: Sony CorporationInventors: Naoki Hirao, Yuya Miura
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Publication number: 20120153294Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: RAYTHEON COMPANYInventors: Ralph Korenstein, Mary K. Herndon, Chae Deok Lee
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Patent number: 8193079Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.Type: GrantFiled: February 9, 2007Date of Patent: June 5, 2012Assignee: The Regents of the University of CaliforniaInventors: John F. Kaeding, Hitoshi Sato, Michael Iza, Hirokuni Asamizu, Hong Zhong, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8187982Abstract: The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.Type: GrantFiled: March 22, 2010Date of Patent: May 29, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Yousuke Ishii, Shingo Okamoto
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Publication number: 20120119218Abstract: A method for forming a single crystalline Group-III Nitride film. A substrate is provided, having a first passivation layer, a monocrystalline layer, and a second passivation layer. The substrate is patterned to form a plurality of features with elongated sidewalls having a second crystal orientation. Group-III Nitride films are formed on the elongated sidewalls, but not on the first or second passivation layers. In one embodiment, the dimensions of the patterned features and the film deposition process result in a single crystalline Group-III Nitride film having a third crystal orientation normal to the substrate surface. In another embodiment, the dimensions and orientation of the patterned features and the film deposition process result in a plurality of single crystalline Group-III Nitride films. In other embodiments, additional layers are formed on the Group-III Nitride film or films to form semiconductor devices, for example, a light-emitting diode.Type: ApplicationFiled: October 31, 2011Publication date: May 17, 2012Applicant: Applied Materials, Inc.Inventor: Jie Su
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Patent number: 8173492Abstract: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.Type: GrantFiled: July 24, 2009Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Je-hun Lee, Chang-oh Jeong, Beom-seok Cho, Yang-ho Bae
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Patent number: 8173494Abstract: A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.Type: GrantFiled: September 24, 2010Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Hong-Sick Park, Joo-Ae Youn, Sun-Young Hong, Bong-Kyun Kim, Won-Suk Shin, Byeong-Jin Lee
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Publication number: 20120074425Abstract: Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.Type: ApplicationFiled: December 1, 2011Publication date: March 29, 2012Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Benjamin A. Haskell, Michael D. Craven, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Publication number: 20120068184Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.Type: ApplicationFiled: November 30, 2011Publication date: March 22, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Michael D. Craven, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 8138064Abstract: A method for producing a silicon film-transferred insulator wafer is disclosed. The method includes a surface activation step of performing a surface activation treatment on at least one of a surface of an insulator wafer and a hydrogen ion-implanted surface of a single crystal silicon wafer into which a hydrogen ion has been implanted to form a hydrogen ion-implanted layer; a bonding step that bonds the hydrogen ion-implanted surface to the surface of the insulator wafer to obtain bonded wafers; a first heating step that heats the bonded wafers; a grinding and/or etching step of grinding and/or etching a surface of a single crystal silicon wafer side of the bonded wafers; a second heating step that heats the bonded wafers; and a detachment step to detach the hydrogen ion-implanted layer by applying a mechanical impact to the hydrogen ion-implanted layer of the bonded wafers thus heated at the second temperature.Type: GrantFiled: October 29, 2009Date of Patent: March 20, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
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Patent number: 8138069Abstract: Embodiments of the present invention relate to apparatus and method for pretreatment of substrates for manufacturing devices such as light emitting diodes (LEDs) or laser diodes (LDs). One embodiment of the present invention comprises pre-treating the aluminum oxide containing substrate by exposing a surface of the aluminum oxide containing substrate to a pretreatment gas mixture, wherein the pretreatment gas mixture comprises ammonia (NH3) and a halogen gas.Type: GrantFiled: April 23, 2010Date of Patent: March 20, 2012Assignee: Applied Materials, Inc.Inventors: Yuriy Melnik, Olga Kryliouk, Hidehiro Kojiri, Tetsuya Ishikawa
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Publication number: 20120064653Abstract: A method for manufacturing a nitride semiconductor device such as a nitride semiconductor light emitting device, a transistor device or the like. The method includes the steps of forming a buffer crystalline layer of the nitride semiconductor made of AlxGayIn1-x-yN (0?x?1, 0?y ?1 and 0?x+y?1), in which both an a-axis and a c-axis are aligned, directly on a substrate lattice-mismatched with the nitride semiconductor without forming an amorphous low temperature buffer layer, by plasma laser deposition(PLD) method, and growing epitaxially the nitride semiconductor layer on the buffer layer so as to form a device such as a nitride semiconductor light emitting diode, by metal organic chemical vapor deposition (MOCVD).Type: ApplicationFiled: September 24, 2011Publication date: March 15, 2012Applicant: ROHM CO., LTD.Inventors: Ken NAKAHARA, Kentaro Tamura
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Patent number: 8120113Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.Type: GrantFiled: January 15, 2010Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Young-Soo Choi, Gyu-Hyun Kim
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Patent number: 8084337Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.Type: GrantFiled: October 27, 2008Date of Patent: December 27, 2011Assignee: QuNano ABInventors: Lars Samuelson, Jonas Ohlsson, Thomas MÃ¥rtensson, Patrik Svensson
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Patent number: 8076675Abstract: An LED chip includes a substrate and a p-n junction type semiconductor light-emitting structure. The substrate has a first surface and a second surface opposite to the second surface. The p-n junction type semiconductor light-emitting structure is arranged on the first surface of the substrate. A plurality of blind holes is defined in the second surface of the substrate and extends from the second surface towards the first surface. A heat conductive material is filled in each of the plurality of blind holes thereby forming a plurality of heat conductive poles in the plurality of blind holes.Type: GrantFiled: December 30, 2009Date of Patent: December 13, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Da-Wei Lin
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Publication number: 20110278585Abstract: Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.Type: ApplicationFiled: November 16, 2010Publication date: November 17, 2011Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Benjamin A. Haskell, Michael D. Craven, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 8048701Abstract: The present invention relates to a nitride semiconductor light emitting device using a hybrid buffer layer and a method for fabricating the same which can minimize the lattice mismatch between a buffer layer and a nitride semiconductor. The method for fabricating the nitride semiconductor light emitting device using the hybrid buffer layer includes a first step of forming an AlxGa1-xN(0?x<1) layer on a substrate, a second step of forming a three-dimensional crystal seed layer made of a material included in a general formula of AlxGa1-xN(0?x<1) and AlOyNz on the substrate by recrystallizing the substrate with the AlxGa1-xN(0?x<1) layer thereon, and a third step of forming an AlN nanostructure by annealing the substrate subjected to the second step at NH3 gas atmosphere, thus forming a hybrid buffer layer composed of the three-dimensional crystal seed layer and the AlN nanostructure on the substrate.Type: GrantFiled: February 5, 2009Date of Patent: November 1, 2011Assignee: Wooree Lst Co. LtdInventors: Youngkyn Noh, Jae-Eung Oh
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Patent number: 8048786Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.Type: GrantFiled: November 3, 2008Date of Patent: November 1, 2011Assignee: National Central UniversityInventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu
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Publication number: 20110244667Abstract: A method of manufacturing a semiconductor device including a nitride semiconductor layer having high-precision thickness is provided. The method includes steps of: forming a gallium nitride (GaN) layer whose main face is a +c face on a substrate; forming a trench by selectively etching down a partial region in the +c face of the GaN layer; forming a metal layer so as to bury the trench; and separating the substrate and the GaN layer, after that, polishing a ?c face of the GaN layer until the metal layer is exposed, and removing a part in a thickness direction of the GaN layer.Type: ApplicationFiled: March 22, 2011Publication date: October 6, 2011Applicant: Sony CorporationInventors: Naoki Hirao, Yuya Miura
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Patent number: 8022422Abstract: A display apparatus includes pixel electrodes disposed on a first base substrate, a second base substrate which faces the first base substrate, color pixels disposed on the second base substrate, the color pixels correspond to the pixel electrodes in a one-to-one correspondence, each color pixel partially covers the corresponding pixel electrode, a common electrode disposed on the second base substrate to cover the pixel electrodes and an electrophoretic layer including a plurality of electrophoretic particles, the electrophoretic layer being interposed between the pixel electrodes and the common electrode.Type: GrantFiled: July 19, 2010Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Il Kim, Son-Uk Lee, Nam-Seok Roh, Jeong-Kuk Lee
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Patent number: 8017415Abstract: Thin freestanding nitride films are used as a growth substrate to enhance the optical, electrical, mechanical and mobility of nitride based devices and to enable the use of thick transparent conductive oxides. Optoelectronic devices such as LEDs, laser diodes, solar cells, biomedical devices, thermoelectrics, and other optoelectronic devices may be fabricated on the freestanding nitride films. The refractive index of the freestanding nitride films can be controlled via alloy composition. Light guiding or light extraction optical elements may be formed based on freestanding nitride films with or without layers. Dual sided processing is enabled by use of these freestanding nitride films. This enables more efficient output for light emitting devices and more efficient energy conversion for solar cells.Type: GrantFiled: November 4, 2009Date of Patent: September 13, 2011Assignee: Goldeneye, Inc.Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
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Publication number: 20110198560Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.Type: ApplicationFiled: February 13, 2009Publication date: August 18, 2011Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
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Patent number: 7981711Abstract: A manufacture method of a multilayer structure having a non-polar a-plane {11-22} III-nitride layer includes forming a nucleation layer on a r-plane substrate, wherein the nucleation layer is composed of multiple nitride layers; and forming a non-polar a-plane {11-20} III-nitride layer on the nucleation layer. The nucleation layer features reduced stress, reduced phase difference of lattice, blocked elongation of dislocation, and reduced density of dislocation. Thus, the non-polar a-plane {11-20} III-nitride layer with flat surface can be formed.Type: GrantFiled: May 19, 2009Date of Patent: July 19, 2011Assignee: National Chiao Tung UniversityInventors: Wei-I Lee, Jenn-Fang Chen, Chen-Hao Chiang
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Patent number: 7977673Abstract: To provide a semiconductor layer in which a GaN system epitaxial layer having high crystal quality can be obtained. The semiconductor layer includes a ?-Ga2O3 substrate 1 made of a ?-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the ?-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD method. Since lattice constants of the GaN layer 2 and the GaN growth layer 3 match each other, and the GaN growth layer 3 grows so as to succeed to high crystalline of the GaN layer 2, the GaN growth layer 3 having high crystalline is obtained.Type: GrantFiled: August 4, 2004Date of Patent: July 12, 2011Assignee: Koha Co., Ltd.Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Patent number: 7951685Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Sumitomo Chemical Company, LimitedInventors: Hiroyuki Sazawa, Naohiro Nishikawa, Masahiko Hata
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Patent number: 7939433Abstract: A method for producing a nitride semiconductor laser light source is provided. The nitride semiconductor laser light source has a nitride semiconductor laser chip, a stem for mounting the laser chip thereon, and a cap for covering the laser chip. The laser chip is encapsulated in a sealed container composed of the stem and the cap. The method for producing this nitride semiconductor laser light source has a cleaning step of cleaning the surface of the laser chip, the stem, or the cap. In the cleaning step, the laser chip, the stem, or the cap is exposed with ozone or an excited oxygen atom, or baked by heat. The method also has, after the cleaning step, a capping step of encapsulating the laser chip in the sealed container composed of the stem and the cap. During the capping step, the cleaned surface of the laser chip, the stem, or the cap is kept clean.Type: GrantFiled: February 16, 2010Date of Patent: May 10, 2011Assignee: Sharp Kabushiki KaishaInventors: Daisuke Hanaoka, Masaya Ishida, Atsushi Ogawa, Yoshihiko Tani, Takuro Ishikura
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Patent number: 7939929Abstract: A semiconductor laser device includes a supporting substrate; a semiconductor laser device portion which is formed on a surface of the supporting substrate, and which includes a pair of cavity surfaces; an adhesive layer with which the supporting substrate and the semiconductor laser device portion are adhered to each other; and areas, in which no adhesive layer exists, the areas being near the ends respectively of the cavity surfaces, the ends being closer to the supporting substrate.Type: GrantFiled: September 29, 2006Date of Patent: May 10, 2011Assignee: Sanyo Electric Co., Ltd.Inventor: Masayuki Hata
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Patent number: 7919815Abstract: Wafer suitable for semiconductor deposition application can be fabricated to have low bow, warp, total thickness variation, taper, and total indicated reading properties. The wafers can be fabricated by cutting a boule to produce rough-cut wafers, lapping the rough-cut wafers, etching the lapped wafers to remove a defect, deformation zone and relieve residual stress, and chemically mechanically polishing the etched wafers to desired finish properties. Etching can be performed by immersion in a heated etching solution comprising sulfuric acid or a mixture of sulfuric and phosphoric acids. A low pH slurry utilized in chemical mechanical polishing of the spinel wafer can comprise ?-Al2O3 and an organic phosphate.Type: GrantFiled: March 1, 2006Date of Patent: April 5, 2011Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventors: Brahmanandam Tanikella, Elizabeth Thomas, Frank L. Csillag, Palaniappan Chinnakaruppan, Jadwiga Jaroniec, Eric Virey, Robert A. Rizzuto
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Patent number: 7915636Abstract: The present disclosure relates to a III-nitride semiconductor light emitting device which improves external quantum efficiency by using a p-type nitride semiconductor layer with a rough surface, the p-type nitride semiconductor layer including: a first nitride semiconductor layer with a first doping concentration, a second nitride semiconductor layer with a second doping concentration lower than the first doping concentration and with the rough surface, and a third nitride semiconductor layer with a higher doping concentration than a second doping concentration.Type: GrantFiled: August 21, 2008Date of Patent: March 29, 2011Assignee: Epivalley Co., Ltd.Inventor: Chang Myung Lee
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Patent number: 7892934Abstract: On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate.Type: GrantFiled: November 1, 2006Date of Patent: February 22, 2011Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Shoji Akiyama
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Patent number: 7875932Abstract: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.Type: GrantFiled: October 19, 2009Date of Patent: January 25, 2011Assignee: Intel CorporationInventors: Been-Yih Jin, Reza Arghavani, Robert Chau
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Patent number: 7867881Abstract: A method for manufacturing a nitride semiconductor substrate including the steps of: forming a nitride semiconductor layer on a sapphire substrate, and manufacturing a freestanding nitride semiconductor substrate by using the nitride semiconductor layer separated from the sapphire substrate, wherein variability of inclinations of the C-axes, being a difference between a maximum value and a minimum value of inclination of the C-axes in a radially-outward direction at each point on a front surface of the sapphire substrate is 0.3° or more and 1° or less.Type: GrantFiled: March 4, 2009Date of Patent: January 11, 2011Assignee: Hitachi Cable, Ltd.Inventors: Takeshi Meguro, Takayuki Suzuki, Ken Ikeda
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Patent number: 7855087Abstract: This sheet production apparatus comprises a vessel defining a channel configured to hold a melt. The melt is configured to flow from a first point to a second point of the channel. A cooling plate is disposed proximate the melt and is configured to form a sheet on the melt. A spillway is disposed at the second point of the channel. This spillway is configured to separate the sheet from the melt.Type: GrantFiled: March 12, 2009Date of Patent: December 21, 2010Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Peter L. Kellerman, Frank Sinclair
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Patent number: 7829435Abstract: A GaN-based thin film (thick film) is grown using a metal buffer layer grown on a substrate. (a) A metal buffer layer (210) made of, for example, Cr or Cu is vapor-deposited on a sapphire substrate (120). (b) A substrate obtained by vapor-depositing the metal buffer layer (210) on the sapphire substrate (120) is nitrided in an ammonia gas ambient, thereby forming a metal nitride layer (212). (c) A GaN buffer layer (222) is grown on the nitrided metal buffer layers (210, 212). (d) Finally, a GaN single-crystal layer (220) is grown. This GaN single-crystal layer (220) can be grown to have various thicknesses depending on the objects. A freestanding substrate can be fabricated by selective chemical etching of the substrate fabricated by the above steps. It is also possible to use the substrate fabricated by the above steps as a GaN template substrate for fabricating a GaN-based light emitting diode or laser diode.Type: GrantFiled: August 21, 2009Date of Patent: November 9, 2010Assignees: Tohoku Techno Arch Co., Ltd., Furukawa Co., Ltd., Mitsubishi Chemical Corporation, Dowa Holdings Co., Ltd., Epivalley Co., Ltd., Wavesquare Inc.Inventors: Takafumi Yao, Meoung-Whan Cho
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Publication number: 20100273318Abstract: Embodiments of the present invention relate to apparatus and method for pretreatment of substrates for manufacturing devices such as light emitting diodes (LEDs) or laser diodes (LDs). One embodiment of the present invention comprises pre-treating the aluminum oxide containing substrate by exposing a surface of the aluminum oxide containing substrate to a pretreatment gas mixture, wherein the pretreatment gas mixture comprises ammonia (NH3) and a halogen gas.Type: ApplicationFiled: April 23, 2010Publication date: October 28, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Yuriy Melnik, Olga Kryliouk, Hidehiro Kojiri, Tetsuya Ishikawa
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Patent number: 7816678Abstract: Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer to a predetermined thickness on a crystal growth plate; depositing a buffer layer on the single crystalline silicon layer; forming a partition layer at a predetermined depth in the single crystalline silicon layer by, e.g., implanting hydrogen ions in the single crystalline silicon layer from an upper portion of an insulating layer; attaching a substrate to the buffer layer; and releasing the partition layer of the single crystalline silicon layer by heating the partition layer from the crystal growth plate to obtain a single crystalline silicon layer of a predetermined thickness on the substrate.Type: GrantFiled: July 18, 2008Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Takashi Noguchi, Wenxu Xianyu, Huaxiang Yin
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Patent number: 7799651Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.Type: GrantFiled: June 30, 2008Date of Patent: September 21, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Carlos Mazure, Ian Cayrefourcq, Konstantin Bourdelle
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Patent number: 7785918Abstract: An image device which includes reflowed color filters. Reflowed color filters may be formed by heat treating preliminary color filters. When preliminary color filters are reflowed, color filters of different colors may be formed continuous with each other. Contiguous color filters in an image device may reduce manufacturing costs, maximize optical efficiency, minimize noise, and/or minimize crosstalk.Type: GrantFiled: July 10, 2007Date of Patent: August 31, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Young-Je Yun
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Patent number: 7781242Abstract: A method of forming a vertical structure light emitting diode with a heat exhaustion structure, comprising the steps of: providing a sapphire substrate; producing a number of recesses on the sapphire substrate, each of which has a depth of p; forming a buffer layer having a number of protrusions, each of which has a height of q smaller than p so that when the protrusions of the buffer layer are accommodated within the recesses of the sapphire substrate, a number of gaps are formed therebetween for heat exhaustion; growing a number of luminescent layers on the buffer layer, having a medium layer formed between the luminescent layers and the buffer layer; etching through the luminescent layers and the buffer layer to form a duct for heat exhaustion; removing the sapphire substrate by excimer laser lift-off (LLO); roughening the medium layer; and depositing electrodes on the roughened medium layer.Type: GrantFiled: December 10, 2009Date of Patent: August 24, 2010Assignee: Walsin Lihwa CorporationInventors: Shiue-Lung Chen, Jeng-Kuo Feng, Ching-Hwa Chang Jean, Jang-Ho Chen
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Patent number: 7776740Abstract: A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.Type: GrantFiled: January 22, 2008Date of Patent: August 17, 2010Assignee: Tokyo Electron LimitedInventors: Kenji Suzuki, Miho Jomen, Jonathan Rullan
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Patent number: 7754504Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.Type: GrantFiled: May 16, 2006Date of Patent: July 13, 2010Assignee: Sony CorporationInventors: Akira Ohmae, Shigetaka Tomiya, Yuki Maeda, Michinori Shiomi, Takaaki Ami, Takao Miyajima, Katsunori Yanashima, Takashi Tange, Atsushi Yasuda
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Patent number: 7745245Abstract: At least one recess and/or protruding portion is created on the surface portion of a substrate for scattering or diffracting light generated in a light emitting region. The recess and/or protruding portion has a shape that prevents crystal defects from occurring in semiconductor layers.Type: GrantFiled: January 30, 2008Date of Patent: June 29, 2010Assignee: Nichia CorporationInventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
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Publication number: 20100133663Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface.Type: ApplicationFiled: February 1, 2010Publication date: June 3, 2010Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
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Patent number: 7727790Abstract: The invention is method for fabricating light emitting diodes. A layered semiconductor structure is provided on a growth substrate. The method includes using a pulsed laser to form an interfacial layer between the layered semiconductor structure and the growth substrate for subsequent substrate detachment and to simultaneously form light extracting elements on the layered semiconductor structure. The method reduces the number of steps required to fabricate a light emitting diode.Type: GrantFiled: January 29, 2008Date of Patent: June 1, 2010Assignee: Goldeneye, Inc.Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay, Richard L. Rose
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Patent number: 7700423Abstract: A method of fabricating an epitaxial compound semiconductor III-V wafer suitable for the subsequent fabrication of at least two different types of integrated active devices (such as an HBT and a FET) on such wafer by providing a substrate; growing a first epitaxial structure on the substrate; and growing a second epitaxial structure on the first epitaxial structure.Type: GrantFiled: July 28, 2006Date of Patent: April 20, 2010Assignee: IQE RF, LLCInventors: Paul Cooke, Richard W. Hoffman, Jr., Victor Labyuk, Sherry Qianwen Ye