Heteroepitaxy (epo) Patents (Class 257/E21.124)
  • Patent number: 8809908
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: August 19, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata
  • Patent number: 8754419
    Abstract: A semiconductor device includes a Si substrate having a principal plane that is a crystal surface inclined at an off angle of 0.1 degrees or less with respect to a (111) plane, an AlN layer that is provided so as to contact the principal plane of the Si substrate and is configured so that an FWHM of a rocking curve of a (002) plane by x-ray diffraction is not greater than 2000 seconds, and a GaN-based semiconductor layer formed on the AlN layer.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 17, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken Nakata, Isao Makabe, Keiichi Yui, Takamitsu Kitamura
  • Patent number: 8664084
    Abstract: A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: March 4, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Chrystel Deguet, Laurent Clavelier
  • Patent number: 8609451
    Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Crystal Solar Inc.
    Inventors: Tirunelveli S. Ravi, Ashish Asthana
  • Patent number: 8476101
    Abstract: A method of making a semiconductor radiation detector includes the steps of providing a semiconductor substrate having front and rear major opposing surfaces, forming a solder mask layer over the rear major surface, patterning the solder mask layer into a plurality of pixel separation regions, and after the step of patterning the solder mask layer, forming anode pixels over the rear major surface. Each anode pixel is formed between adjacent pixel-separation regions and a cathode electrode is located over the front major surface of the substrate. The solder mask can be used as a permanent photoresist in developing patterned electrodes on CdZnTe/CdTe devices as well as a permanent reliability protection coating. The method is very robust and ensures long-term reliability, outstanding detector performance, and may be used in applications such as medical imaging and for demanding other highly spectroscopic applications.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 2, 2013
    Assignee: Redlen Technologies
    Inventors: Henry Chen, Pramodha Marthandam, Salah Awadalla, Pinghe Lu
  • Patent number: 8378385
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 19, 2013
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Patent number: 8293553
    Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 23, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Illek, Wilhelm Stein, Robert Walter, Ralph Wirth
  • Patent number: 8188573
    Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 29, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Suh-Fang Lin, Wei-Hung Kuo
  • Patent number: 8093625
    Abstract: Disclosed is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a buffer layer having a super-lattice layer on a silicon substrate, a first conductive clad layer on the buffer layer, an active layer on the first conductive clad layer, and a second conductive clad layer on the active layer.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: January 10, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sang Kyun Shim
  • Patent number: 7964945
    Abstract: A glass cap molding package includes a substrate with an external connection terminal formed on a peripheral region of a top surface; an image sensor mounted on the top surface of the substrate; a transparent member installed on an upper part of the image sensor; and a molding unit formed to seal the image sensor and the transparent member. The mold unit exposes the external connection terminal of the substrate to a lateral surface of the substrate. The glass cap molding package and a manufacturing method thereof and a camera module including the same reduce a manufacturing cost and improve productivity by manufacturing a small module in comparison with a conventional module and simplifying a process.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: June 21, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Mun Ryu, Jung Seok Lee, Hyung Kyu Park, Bo Kyoung Kim, Yun Seok Woo, Jung Jin Kim
  • Patent number: 7915099
    Abstract: The speed of the laser scanned by the scanning means such as a galvanometer mirror or a polygon mirror is not constant in the center portion and in the end portion of the scanning width. As a result, the object, for example an amorphous semiconductor film, is irradiated with the excessive energy and therefore there is a risk that the amorphous semiconductor film is peeled. In the present invention, in the case where the laser spot of the energy beam output continuously on the irradiated object is scanned by moving it back and forth with the use of the scanning means or the like, the beam is irradiated to the outside of the element-forming region when the scanning speed of the spot is not the predetermined value, for example when the speed is not constant, and accelerates, decelerates, or is zero, for example in the positions where the scanning direction changes, or where the scanning starts or ends.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka, Hidekazu Miyairi
  • Patent number: 7785989
    Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 31, 2010
    Assignee: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Arthur Cornfeld, Tansen Varghese, Fred Newman, Jacqueline Diaz
  • Patent number: 7772127
    Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: August 10, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Christophe Figuet, Mark Kennard
  • Patent number: 7700447
    Abstract: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 20, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Ilija Dukovski, Robert John Stephenson, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Robert J. Mears, Xiangyang Huang, Marek Hytha
  • Patent number: 7691657
    Abstract: A nitride based 3-5 group compound semiconductor light emitting device comprising: a substrate; a buffer layer formed above the substrate; a first In-doped GaN layer formed above the buffer layer; an InxGa1-xN/InyGa1?yN super lattice structure layer formed above the first In-doped GaN layer; a first electrode contact layer formed above the InxGa1-31 xN/InyGa1?yN super lattice structure layer; an active layer formed above the first electrode contact layer and functioning to emit light; a second In-doped GaN layer; a GaN layer formed above the second In-doped GaN layer; and a second electrode contact layer formed above the GaN layer. The present invention can reduce crystal defects of the nitride based 3-5 group compound semiconductor light emitting device and improve the crystallinity of a GaN GaN based single crystal layer in order to improve the performance of the light emitting device and ensure the reliability thereof.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: April 6, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7675091
    Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: March 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Kyoo-Chul Cho, Shin-Hyeok Han, Tae-Soo Kang
  • Publication number: 20090155988
    Abstract: A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma and substrate bias voltage. Furthermore, the atom structure of the poly-silicon thin film is aligned in regular arrangement by making use of the induction layer having optimal orientation and lattice constant close to that of the silicon, thus raising the crystallization quality of the poly-silicon thin film and reducing the thickness of the incubation layer.
    Type: Application
    Filed: January 13, 2009
    Publication date: June 18, 2009
    Inventors: I-Hsuan PENG, Chin-jen HUANG, Liang-Tang WANG, Jung-Fang CHANG, Te-Chi WONG
  • Patent number: 7459374
    Abstract: A method for manufacturing a semiconductor heterostructure by first manufacturing a donor wafer having a first substrate with a first in-plane lattice parameter, a spatially graded buffer layer having a second in-plane lattice parameter, and a strained smoothing layer of a semiconductor material having a third in-plane lattice parameter which has a value between that of the first and second lattice parameters. A top layer is formed on the ungraded layer a top layer of a semiconductor material having a top surface, optionally with a superficial layer present on the top surface and having a thickness that is equal to or smaller than 10 nanometers. Next, a handle wafer of a second substrate having an insulator layer thereon is bonded with the donor wafer in such way that (a) the insulator layer of the handle wafer is bonded directly onto the top surface of the top layer of the donor wafer, or (b) the insulator layer of the handle wafer is bonded onto the superficial layer.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: December 2, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Cécile Aulnette, Christophe Figuet, Nicolas Daval