Bonding Of Semiconductor Wafer To Insulating Substrate Or To Semic Onducting Substrate Using An Intermediate Insulating Layer (epo) Patents (Class 257/E21.122)
  • Patent number: 10910256
    Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 2, 2021
    Assignee: Soitec
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Patent number: 10847490
    Abstract: An apparatus includes an alignment module configured to align a first wafer and a second wafer based on alignment markers on the first wafer and corresponding alignment markers on the second wafer. The apparatus further includes a flag placement module configured to insert a plurality of flags between the first wafer and the second wafer, a flag-out mechanism configured to simultaneously move the plurality of flags to a flag-out position, and a controller configured to determine whether the wafers remain aligned within an alignment tolerance based on an amount of time for each flag of the plurality of flags to reach the flag-out position.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
  • Patent number: 10811381
    Abstract: A wafer to wafer bonding method includes performing a plasma process on a bonding surface of a first wafer, pressurizing the first wafer after performing the plasma process on the bonding surface of the first wafer, and bonding the first wafer to a second wafer. The plasma process has different plasma densities along a circumferential direction about a center of the first wafer. A middle portion of the first wafer protrudes after pressurizing the first wafer. The first wafer is bonded to the second wafer by gradually joining the first wafer to the second wafer from the middle portion of the first wafer to a peripheral region of the first wafer.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Ho Lee, Sung-Hyup Kim, Ki-Ju Sohn
  • Patent number: 10784348
    Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 22, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Alan Fanelli, Richard Hammond
  • Patent number: 10707068
    Abstract: The present invention relates to a method for producing solid body layers. The claimed method comprises at least the following steps: providing a solid body (2) for separating at least one solid body layer (4), arranging a receiving layer (10) on the solid body for holding the solid body layer (4), said receiving layer being made of at least one polymer and an additional material, said receiving layer, in terms of volume, be made mainly of polymer, the additional material having a greater conductivity than the polymer, and the receiving layer (10) is subjected to thermal stress, in particular, mechanical stress, for generating voltages in the solid body (2), wherein a crack in the solid body (2) along a separation plane (8) expands due to the voltages, the solid layer (4) being separated from the solid body (2) due to the crack.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 7, 2020
    Assignee: Siltectra GmbH
    Inventors: Jan Richter, Christian Beyer, Anas Ajaj
  • Patent number: 10703627
    Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: July 7, 2020
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ludovic Ecarnot
  • Patent number: 10707190
    Abstract: A backplane can have a non-planar top surface. Insulating material portions including planar top surface regions located within a same horizontal plane are formed over the backplane. A two-dimensional array of metal plate clusters is formed over the insulating material portions. Each of the metal plate clusters includes a plurality of metal plates. Each metal plate includes a horizontal metal plate portion overlying a planar top surface region and a connection metal portion connected to a respective metal interconnect structure in the backplane. A two-dimensional array of light emitting device clusters is bonded to the backplane through respective bonding structures. Each light emitting device cluster includes a plurality of light emitting devices overlying a respective metal plate cluster.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 7, 2020
    Assignee: GLO AB
    Inventors: Tsun Lau, Fariba Danesh, Timothy Gallagher, Anusha Pokhriyal
  • Patent number: 10644115
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a base layer, and a crystalline oxide film including a corundum structure and including an r-plane as a principal plane. The crystalline oxide film is directly arranged on the base layer or through at least one layer that is adjacently arranged to the base layer, and the crystalline oxide film is with a full width at half maximum (FWHM) of rocking curve that is 0.1° or less by ?-scan X-ray diffraction (XRD) measurement.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 5, 2020
    Assignee: FLOSFIA INC.
    Inventors: Takayoshi Oshima, Takashi Shinohe, Isao Takahashi
  • Patent number: 10636688
    Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hung Wang, Ping-Yin Liu, Yeong-Jyh Lin, Yeur-Luen Tu
  • Patent number: 10607515
    Abstract: The present disclosure relates to a display device using semiconductor light emitting devices and a fabrication method thereof, and the display device according to the present disclosure can include a plurality of semiconductor light emitting devices, a first wiring electrode and a second wiring electrode respectively extended from the semiconductor light emitting devices to supply an electric signal to the semiconductor light emitting devices, a plurality of pair electrodes disposed on the substrate, and provided with a first electrode and a second electrode configured to generate an electric field when an electric current is supplied, and a dielectric layer formed to cover the pair electrodes, wherein the first wiring electrode and the second wiring electrode are formed on an opposite side to the plurality of the pair electrodes with respect to the semiconductor light emitting devices.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 31, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Changseo Park, Seongmin Moon, Bongchu Shim, Kiseong Jeon, Hyunwoo Cho
  • Patent number: 10396054
    Abstract: An apparatus includes a bonding system configured to bond at least two wafers. The bonding system has a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers. The apparatus also includes sensors configured to detect data related to a flag-out condition of the flags of the plurality of flag. The apparatus further includes at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
  • Patent number: 10304812
    Abstract: An optoelectronic device including a first integrated circuit that includes:—a substrate, having first and second opposite surfaces; and—groups of sets of light-emitting diodes resting on the first surface. The integrated circuit also includes:—in the substrate, first side elements for electrically insulating portions of the substrate around each set; and—for each group on the second surface, at least one first conductive contact, connected to the first terminal of the group, and one second conductive contact, connected to the second terminal of the group. The device includes a second integrated circuit containing:—third and fourth opposite surfaces; and—third conductive contacts, located on the third surface and electrically connected to the first and second conductive contacts. The first integrated circuit is attached onto the third surface of the second integrated circuit.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 28, 2019
    Assignee: Aledia
    Inventors: Frédéric Mercier, Philipe Gilet, Xavier Hugon
  • Patent number: 10304739
    Abstract: A method for manufacturing a semiconductor substrate according to the present invention includes preparing a seed substrate containing a semiconductor material, forming an ion implanted layer at a certain depth from a front surface of a main surface of the seed substrate by implanting ions into the seed substrate, growing a semiconductor layer on the main surface of the seed substrate with a vapor-phase synthesis method, and separating a semiconductor substrate including the semiconductor layer and a part of the seed substrate by irradiating the front surface of the main surface of at least any of the semiconductor layer and the seed substrate with light.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: May 28, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshiki Nishibayashi, Kazuo Nakamae
  • Patent number: 10290674
    Abstract: A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 14, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Cem Basceri
  • Patent number: 10276631
    Abstract: A method for producing a micro-LED matrix by (A) depositing an LED layer structure onto a working substrate; (B) singulating a plurality of LED structures from the LED layer structure on the working substrate; (C) applying a first contact-making structure to a carrier substrate; and (D) transferring the plurality of LED structures from the working substrate to the carrier substrate by bonding and laser lift-off. An at least two-layered carrier substrate is used, including a carrier layer and a first flexible polymer layer, in step C the first contact-making structure is applied indirectly or directly to a side of the first polymer layer which faces away from the carrier layer, and in an additional method step D-0 between method steps C and D, a second flexible polymer layer is formed at least between the singulated LED structures. A micro-LED matrix and use are also provided.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 30, 2019
    Assignees: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V., Albert-Ludwigs-Universität Freiburg
    Inventors: Christian Gossler, Ulrich Schwarz, Patrick Ruther
  • Patent number: 10249598
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Pauli Jaervinen, Richard Patten
  • Patent number: 10236205
    Abstract: The present invention provides a kind of thin film and a fabrication method of thin films. The method comprises implanting ions under the surface of the original substrate by ion-implanting method, hence creating a thin film layer, a splitting layer and a remaining material layer on the original substrate; wherein, the thin film layer is on the surface of the original substrate and the splitting layer is between the thin film layer and the remaining material layer; the implanted ions are distributed in the splitting layer. Make the target substrate be in contact with the thin film layer of the original substrate, and then bond the original substrate to the target substrate by wafer-bonding method to form a bonding unit. Place the bonding unit into a prepared container to heat the bonding unit, so that the thin film layer is split off from the remaining material layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 19, 2019
    Assignee: Jinan Jingzheng Electronics Co., Ltd.
    Inventors: Hui Hu, Wen Hu
  • Patent number: 10204838
    Abstract: A handle substrate of a composite substrate for a semiconductor includes a base substrate comprising a polycrystalline material; and an amorphous layer provided over the base substrate, the amorphous layer having chemical resistance and comprising a single component with a high purity.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 12, 2019
    Assignee: NGK INSULATORS, LTD.
    Inventors: Akiyoshi Ide, Tatsuro Takagaki, Sugio Miyazawa, Yasunori Iwasaki
  • Patent number: 10199301
    Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 5, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Julio C. Costa, Baker Scott
  • Patent number: 10177178
    Abstract: An integrated circuit (IC) microdisplay structure is disclosed. The structure can include: a first oxide layer positioned on a substrate; a first voltage source (VSS) pad within the first oxide layer; a metal pillar disposed within the first oxide layer and on the first VSS pad; a first gallium nitride layer disposed on the metal pillar and extending over the first oxide layer; and at least one subpixel formed from the first gallium nitride layer. Alternatively, the structure can include a first oxide layer positioned on a substrate; a first metal layer positioned on the first oxide layer; a first gallium nitride layer on the first metal layer; and at least one subpixel formed from the first gallium nitride layer. The structure may further include a subpixel driver electrically connected to the at least one subpixels where a portion of the subpixel driver is vertically aligned with a subpixel.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOABLFOUNDRIES INC.
    Inventors: Deepak K. Nayak, Srinivasa Banna
  • Patent number: 10170311
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Patent number: 10163748
    Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 25, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Julio C. Costa, Baker Scott
  • Patent number: 10056406
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 21, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Makiyama, Yoshiki Yamamoto
  • Patent number: 10037968
    Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 9941329
    Abstract: Disclosed is a multi-color semiconductor LED display with integrated with CMOS circuit components, such as thin film transistors (TFTs). LEDs of the display are disposed on a first major surface of a substrate while CMOS circuit components which are configured as circuitry for operating the display are disposed on a second opposing major surface of the substrate. The CMOS components and LEDs are coupled by through silicon via (TSV) contacts through the substrate. Integrating CMOS components with LED on one substrate enhances compactness of the display. Other advantages include low power and low cost with high brightness and resolution desired for portable applications, including virtual reality and augmented reality applications.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Deepak Nayak, Srinivasa Banna, Ajey P. Jacob
  • Patent number: 9927391
    Abstract: A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: March 27, 2018
    Inventor: Bao Tran
  • Patent number: 9806284
    Abstract: A bent part is prevented from being damaged by preventing displacement of a bend. A display device includes a circuit substrate having a flat part and a bent part, a light emitting element layer disposed on each of unit pixels forming an image, a circuit layer stacked on an outside surface of the bent part, a sealing layer that covers and seals the light emitting element layer, and a double-sided tape that includes a base material having a first surface and a second surface, respectively provided with a first adhesive and a second adhesive, and is bent at an inside of the bent part of the circuit substrate with the first surface being outside. The first surface sticks to the circuit substrate, and the second surface is folded back and adhered together.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 31, 2017
    Assignee: Japan Display Inc.
    Inventors: Yusuke Goto, Takashi Saeki, Toshihiro Sato
  • Patent number: 9786734
    Abstract: A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 10, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 9786544
    Abstract: Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Paul Grisham
  • Patent number: 9761444
    Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: September 12, 2017
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
  • Patent number: 9728459
    Abstract: A method for singulating an assemblage (1) into a plurality of semiconductor chips (10) is specified, wherein an assemblage comprising a carrier (4), a semiconductor layer sequence (2) and a metallic layer (3) is provided. Separating trenches (45) are formed in the carrier. The assemblage is subjected to mechanical loading, with the result that the metallic layer breaks along the separating trenches and the assemblage is singulated into semiconductor chips, wherein the singulated semiconductor chips each have part of the semiconductor layer sequence, of the carrier and of the metallic layer. A semiconductor chip (10) is furthermore specified.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 8, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Mathias Kaempf
  • Patent number: 9673650
    Abstract: Method for monitoring an electrochemical cell or a battery (1), in particular method for monitoring the first charging of an electrochemical cell or of a battery (1) of Li-ion type, comprising a step of acquiring data relating to acoustic emissions produced in the electrochemical cell or in the battery and, by using the data acquired, a step of detecting: the formation of a passivation film on an electrode of the electrochemical cell or of the battery; and/or the first storage of lithium in an electrode of the electrochemical cell or of the battery.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 6, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITE JOSEPH FOURIER-GRENOBLE, INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Sylvie Genies, David Brun-Buisson, Nina Kircheva, Pierre-Xavier Thivel
  • Patent number: 9640732
    Abstract: Diode includes light emitting region, first metal layer, dielectric layer, and second metal layer. Light emitting diode includes n-type group III-nitride portion, p-type group III-nitride layer, and light emitting region sandwiched between n- and p-type layers. First metal layer may be coupled to p-type III-N portion and plurality of first terminals. First metal layer and p-type III-N portion may have substantially similar lateral size that is smaller than 200 micrometers. A portion of light emitting region and first metal layer may include a single via. Electrically-insulating layer may be coupled to first metal layer and sides of the single via. First terminals may be exposed from electrically-insulating layer. Second metal layer may include second terminal and may be coupled to electrically-insulating layer and to n-type III-N portion through the single via. The thickness of the diode excluding second terminal may be between 2 and 20 micrometers. Other embodiments are described.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: May 2, 2017
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Thomas Wunderer, Christopher L. Chua, Noble M. Johnson
  • Patent number: 9629248
    Abstract: Provided is an embedded printed circuit board, including: a first insulating substrate including a first cavity and a second cavity; a first element disposed in the first cavity; an adhesive layer for adhering the first insulating substrate to the first element and including an opening to which the first element is exposed; and an second insulating substrate forming a bonding layer of a lower surface of the first insulating substrate and a bottom surface of the second cavity.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: April 18, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Deok Soon Kwon, Sang Hyuck Nam, Won Suk Jung
  • Patent number: 9620466
    Abstract: A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 11, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Patent number: 9530986
    Abstract: A light-emitting device includes a transparent substrate, a light-emitting element arranged on or above one main surface of the transparent substrate, and a porous layer arranged on or above the other main surface of the transparent substrate, the porous layer being an organic material layer having a plurality of pores. Inner surfaces of some pores among the plurality of pores may be exposed at a main surface of the porous layer opposite to a side on which the transparent substrate lies. A gas may be present in the pores the inner surfaces of which are exposed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 27, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Kenji Okumoto, Yuji Tanaka
  • Patent number: 9530709
    Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: December 27, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Julio C. Costa, Baker Scott
  • Patent number: 9527721
    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package with an anti-stiction layer, and an associated method of formation. In some embodiments, the MEMS package comprises a device substrate and a CMOS substrate. The device substrate comprises a MEMS device having a moveable or flexible part that is movable or flexible with respect to the device substrate. A surface of the moveable or flexible part is coated by a conformal anti-stiction layer made of polycrystalline silicon. A method for manufacturing the MEMS package is also provided.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chao-Po Lu, Chung-Hsien Hun, Chih-Shan Chen, Chuan-Yi Ko, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Patent number: 9505612
    Abstract: A method for thin film encapsulation (TFE) of a microelectromechanical system (MEMS) device, including providing a substrate; forming a MEMS device on the substrate; forming one or more etching channels adjacent to the MEMS device; providing one or more cavities below the MEMS device; and forming one or more cavities above the MEMS device.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 29, 2016
    Assignee: Agency for Science, Technology and Research
    Inventors: Jae-Wung Lee, Jaibir Sharma, Navab Singh
  • Patent number: 9502627
    Abstract: A light-emitting device includes a first epi-structure with a top surface and a bottom surface opposite to the top surface, a first metal element and a second metal element disposed on the bottom surface, a first through-via, a conductive element disposed on the top surface, and a phosphor layer disposed on the top surface and covering the conductive element. The first epi-structure includes a first doped semiconductor layer, a second doped semiconductor layer closer to the bottom surface than the first doped semiconductor layer, and a light-emitting layer disposed between the first and second doped semiconductor layers. The first through-via extends through the first doped semiconductor layer and the second doped semiconductor layer and is electrically connected to the first doped semiconductor layer and the second metal element. The conductive element is in a configuration to expose a portion of the top surface, and electrically connected to the first through-via.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 22, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 9478496
    Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ming-Tse Lin
  • Patent number: 9453814
    Abstract: A device includes an upper metallic layer, a lower layer, and a nano sensor array positioned between the upper and lower layers to detect a presence of a gas, a chemical, or a biological object, wherein each sensor's electrical characteristic changes when encountering the gas, chemical or biological object.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 27, 2016
    Inventor: Bao Tran
  • Patent number: 9450141
    Abstract: Disclosed are a method for separating a growth substrate, a method for manufacturing a light-emitting diode, and the light-emitting diode. The method for separating a growth substrate, according to one embodiment, comprises: preparing a growth substrate; forming a sacrificial layer and a mask pattern on the growth substrate; etching the sacrificial layer by using electrochemical etching (ECE); covering the mask pattern, and forming a plurality of nitride semiconductor stacking structures which are separated from each other by an element separation area; attaching a support substrate to the plurality of semiconductor stacking structures, wherein the support substrate has a plurality of through-holes connected to the element separation area; and separating the growth substrate from the nitride semiconductor stacking structures.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 20, 2016
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jeong Hun Heo, Joo Won Choi, Choong Min Lee, Young Wug Kim, Su Jin Shin, Su Youn Hong
  • Patent number: 9450098
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9449940
    Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jaspreet S. Gandhi
  • Patent number: 9443802
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 13, 2016
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Patent number: 9406854
    Abstract: Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: August 2, 2016
    Inventors: Mordehai Margalit, Israel Petronius
  • Patent number: 9379000
    Abstract: The present invention relates to a method for producing a nanocarbon film using a hybrid substrate with which a nanocarbon film free from defects can be produced at low cost. This method is characterized in forming an ion implantation region by implanting ion into a single crystal silicon carbide substrate from a surface thereof and after bonding together the surface of the silicon carbide substrate implanted with ion and a surface of a base substrate, releasing the silicon carbide substrate at the ion implanted region to produce a hybrid substrate in which a thin film that includes the single crystal silicon carbide is transferred onto the base substrate, and then heating the hybrid substrate to sublime silicon atoms from the thin film that includes the single crystal silicon carbide so as to obtain the nanocarbon film.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: June 28, 2016
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Makoto Kawai, Yoshihiro Kubota
  • Patent number: 9362255
    Abstract: The invention relates to a method for manufacturing a multilayer strucute on a first substrate, the method including: using the first substrate made of a first material having a Young's modulus Ev and a thickness ev, and using a second substrate covered by the multilayer structure, the second substrate being made of a second material having a Young's modulus Es that is different from the Young's modulus Ev and a thickness es, the thicknesses es and ev complying, plus or minus 10%, with the relation (I); molecularly bonding the first substrate and the multilayer structure together; and removing the second substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 7, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Umberto Rossini, Thierry Flahaut, Vincent Larrey
  • Patent number: 9362348
    Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of fabricating an electronic device comprises: depositing one or more first conductors; and depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: June 7, 2016
    Assignee: NthDegree Technologies Worldwide Inc
    Inventors: Mark David Lowenthal, William Johnstone Ray, Neil O. Shotton, Richard A. Blanchard, Brad Oraw, Mark Allan Lewandowski, Jeffrey Baldridge, Eric Anthony Perozziello