Abstract: Provided is a method for preparing a carbon nanotube/polymer composite material, including: coating a nano-silicon oxide film on the surface of a porous polymer by vacuum coating; depositing a metal catalyst nano-film on the nano-silicon oxide film by vacuum sputtering; growing a carbon nanotube array in situ on the surface of the porous polymer by plasma enhanced chemical vapor deposition to obtain a carbon nanotube/polymer porous material; and impregnating the carbon nanotube/polymer porous material with a polymer and curing to obtain the carbon nanotube/polymer composite material. By using a heat-resistant polymer having a high heat-resistant temperature and a PECVD technique, a carbon nanotube array directly grows in situ on the surface of a polymer at a low temperature, which thereby overcomes the defects of the composites previously prepared, in which carbon nanotubes are difficult to be homogeneously dispersed and the interfacial bonding force in the composites is weak.

Abstract: One example of a heating element includes a first carbon nanotube (CNT) layer and a second CNT layer. At least a portion of the first CNT layer overlaps at least a portion of the second CNT layer, and the first CNT layer includes a first perforated region having a plurality of perforations. Another heating element includes a CNT sheet with a first perforated region having a plurality of perforations and a first perforation density and a second perforated region having a plurality of perforations and a second perforation density different from the first perforation density. A method of forming a heating element includes perforating a first CNT layer so that it includes a perforated region and stacking the first CNT layer with a second CNT layer such that at least a portion of the first CNT layer overlaps at least a portion of the second CNT layer.

Abstract: An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode.

Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.

Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.

Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.

Abstract: A method of forming an amorphous carbon layer on an insulating layer includes the step of forming an amorphous carbon layer using a plasma reaction process. The amorphous carbon layer is formed in an atmosphere containing a plasma excitation gas, a CxHy series gas, a silicon-containing gas, and an oxygen-containing gas.

Abstract: A method for forming an oxide film on a carbon film includes the steps of forming a carbon film on an object to be processed; forming an object-to-be-oxidized layer on the carbon film; and forming an oxide film on the object-to-be-oxidized layer while oxidizing the object-to-be-oxidized layer.

Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

Abstract: The present invention provides a light emitting diode package including: a package mold having a first cavity and a second cavity with a smaller size than that of the first cavity; first and second electrode pads provided on the bottom surfaces of the first cavity and the second cavity, respectively; an LED chip mounted on the first electrode pad; a wire for providing electrical connection between the LED chip and the second electrode pad; and a molding material filled within the first cavity and the second cavity.

Abstract: A method for making a thin film transistor, the method includes the steps of: providing a plurality of carbon nanotubes and an insulating substrate; flocculating the carbon nanotubes to acquire a carbon nanotube structure, applying the carbon nanotube structure on the insulating substrate; forming a source electrode, a drain electrode, and a gate electrode; and covering the carbon nanotube structure with an insulating layer. The source electrode and the drain electrode are connected to the carbon nanotube structure, the gate electrode is electrically insulated from the carbon nanotube structure by the insulating layer.

Abstract: A method of producing a thin film transistor includes a gate electrode formation step that forms a gate electrode on a substrate, a gate insulating layer formation step that forms a gate insulating layer on the substrate in such a manner as to cover the gate electrode formed in the gate electrode formation step, a source/drain electrodes formation step that forms a source electrode and a drain electrode on the gate insulating layer, and a semiconductor layer formation step that applies an aqueous solution for semiconductor layer formation which is an aqueous solution comprising at least a single wall carbon nanotube and a surfactant between the source electrode and the drain electrode formed in the source/drain electrodes formation step by a coating process to form a semiconductor layer comprising the single wall carbon nanotube.

Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described. The MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method may include forming a metal seal on the substrate proximate to a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.

Abstract: Multi-layered carbon-based hardmask and method to form the same. The multi-layered carbon-based hardmask includes at least top and bottom carbon-based hardmask layers having different refractive indexes. The top and bottom carbon-based hardmask layer thicknesses and refractive indexes are tuned so that the top carbon-based hardmask layer serves as an anti-reflective coating (ARC) layer.

Abstract: A display device includes a pixel including: a gate line; a gate insulating film; a substrate; a data line; a pixel electrode; a semiconductor layer formed on the gate line and the gate insulating film; a protective film formed on the data line, the pixel electrode, and the semiconductor layer; and a thin film transistor. A portion of the gate line also serves as a gate electrode of the thin film transistor. A portion of the data line also serves as a drain electrode of the thin film transistor. A portion of the pixel electrode also serves as a source electrode of the thin film transistor. The semiconductor layer is formed of an oxide semiconductor layer. The oxide semiconductor layer is directly connected to the drain electrode and the source electrode, and the data line and the pixel electrode are formed of different conductive films.

Abstract: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without any conventional protective cover. The DLC film is less scratchable and less stainable. Since the fingerprint detection device has no protective cover, the device can be provided in a thin and compact form. In addition, the device has high reliability.

Abstract: An electronic device comprises a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and a at least one epitaxial layer of graphene is disposed on the single crystal region. In a currently preferred embodiment, the single crystal region comprises multilayered hexagonal BN. A method of making such an electronic device comprises the steps of: (a) providing a body including a single crystal region on a major surface of the body. The single crystal region has a hexagonal crystal lattice that is substantially lattice-matched to graphene, and (b) epitaxially forming a at least one graphene layer on that region. In a currently preferred embodiment, step (a) further includes the steps of (a1) providing a single crystal substrate of graphite and (a2) epitaxially forming multilayered single crystal hexagonal BN on the substrate.

Abstract: A method for direct molecular adhesion of an electronic compound (6) on a polymer (4) is described. The polymer (4) is coated with a bonding layer (5), for example silicon oxide, which enables the problems caused by the presence of hydrocarbons to be overcome. The method makes it possible to produce adhesive-free three-dimensional structures (10).

Abstract: Method and system for providing a dynamically reconfigurable display having nanometer-scale resolution, using a patterned array of multi-wall carbon nanotube (MWCNT) clusters. A diode, phosphor or other light source on each MWCNT cluster is independently activated, and different color light sources (e.g., red, green, blue, grey scale, infrared) can be mixed if desired. Resolution is estimated to be 40-100 nm, and reconfiguration time for each MWCNT cluster is no greater than one microsecond.

Abstract: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material.

Abstract: A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer, and (c) causing the carbon nanotubes to grow by heating the catalyst layer by thermal CVD so that the carbon nanotubes serve as the interconnection part. The growth mode control layer is formed by sputtering or vacuum deposition in an atmospheric gas, using a metal selected from a group of Ti, Mo, V, Nb, and W. The growth mode is controlled in accordance with a predetermined concentration of oxygen gas of the atmospheric gas.

Abstract: Method and system for fabricating an array of two or more carbon nanotube (CNT) structures on a coated substrate surface, the structures having substantially the same orientation with respect to a substrate surface. A single electrode, having an associated voltage source with a selected voltage, is connected to a substrate surface after the substrate is coated and before growth of the CNT structures, for a selected voltage application time interval. The CNT structures are then grown on a coated substrate surface with the desired orientation. Optionally, the electrode can be disconnected before the CNT structures are grown.

Abstract: A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm3, a pore diameter of less than 0.1 mm and an internal surface area of the pores which is greater than 10,000 cm2/cm3. Semiconductor wafers having front surface coated by chemical vapor deposition (CVD) and a polished or etched back surface, prepared using the gas-permeable susceptor, have a nanotopography of the back surface, expressed as the PV (=peak to valley) height fluctuation, of less than 5 nm, and at the same time the halo of the back surface, expressed as haze, is less than 5 ppm.