Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

Abstract: The present disclosure generally relates to thin film liftoff processes for use in making devices such as electronic and optoelectronic devices, e.g., photovoltaic devices. The methods described herein use a combination of epitaxial liftoff and spalling techniques to quickly and precisely control the separation of an epilayer from a growth substrate. Provided herein are growth structures having a sacrificial layer positioned between a growth substrate and a sacrificial layer. Exemplary methods of the present disclosure include forming at least one notch in the sacrificial layer and spalling the growth structure by crack propagation at the at least one notch to separate the epilayer from the growth substrate.

Abstract: A method is provided for producing a microelectronic device provided with different strained areas in a superficial layer of a semi-conductor on insulator type substrate, including amorphizing a region of the superficial layer and then a lateral recrystallization of the region from crystalline areas adjoining the region.

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract: A fabricating method of a strained FET includes providing a semiconductive layer having a gate structure disposed thereon, wherein an epitaxial layer is embedded in the semiconductive layer aside the gate structure. Later, an element supply layer is formed to contact the epitaxial layer, wherein the element supply layer and the epitaxial layer have at least one identical element besides silicon. Finally, a thermal process is performed to drive the element into the epitaxial layer.

Abstract: A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.

Abstract: A semiconductor structure is provided in which the diffusion of arsenic is retarded. The structure includes a strain relaxed silicon germanium alloy buffer layer located on a surface of a silicon substrate. A boron-containing p-well region is located in a first region of a carbon doped silicon germanium alloy layer and on a first portion of the strain relaxed silicon germanium alloy buffer layer, and a phosphorus-containing n-well region is located in a second region of the carbon doped silicon germanium alloy layer and on a second portion of the strain relaxed silicon germanium alloy buffer layer. A tensily strained silicon material is located on a surface of the p-well region, and a compressively strained germanium-containing material is located on a surface of the n-well region.

Abstract: Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.

Abstract: The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.

Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.

Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.

Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.

Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.

Abstract: A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.

Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.

Abstract: A method for fabricating a P-type polycrystalline silicon-germanium structure comprises steps: forming an aluminum layer and an amorphous germanium layer on a P-type monocrystalline silicon substrate in sequence; annealing the P-type monocrystalline silicon substrate, the aluminum layer and the amorphous germanium layer at a temperature of 400-650° C.; and undertaking an aluminum-induced crystallization process in which germanium atoms of the amorphous germanium layer and silicon atoms of the P-type monocrystalline silicon substrate simultaneously pass through the aluminum layer and then the amorphous germanium layer being induced and converted into a P-type polycrystalline silicon-germanium layer between the P-type monocrystalline silicon substrate and the aluminum layer. The present invention is a simple, reliable and low-cost method to fabricate a P-type polycrystalline silicon-germanium layer on a P-type monocrystalline silicon substrate.

Abstract: In a manufacture method for a photovoltaic module, a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel is simultaneously pasted on a solar cell. In particular, the manufacture method is implemented by performing the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.

Abstract: To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.

Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

Abstract: A method for fabricating a P-type polycrystalline silicon-germanium structure comprises steps: forming an aluminum layer and an amorphous germanium layer on a P-type monocrystalline silicon substrate in sequence; annealing the P-type monocrystalline silicon substrate, the aluminum layer and the amorphous germanium layer at a temperature of 400-650° C.; and undertaking an aluminum-induced crystallization process in which germanium atoms of the amorphous germanium layer and silicon atoms of the P-type monocrystalline silicon substrate simultaneously pass through the aluminum layer and then the amorphous germanium layer being induced and converted into a P-type polycrystalline silicon-germanium layer between the P-type monocrystalline silicon substrate and the aluminum layer. The present invention is a simple, reliable and low-cost method to fabricate a P-type polycrystalline silicon-germanium layer on a P-type monocrystalline silicon substrate.

Abstract: To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Abstract: A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

Abstract: The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.

Abstract: A method for forming a single crystalline Group-III Nitride film. A substrate is provided, having a first passivation layer, a monocrystalline layer, and a second passivation layer. The substrate is patterned to form a plurality of features with elongated sidewalls having a second crystal orientation. Group-III Nitride films are formed on the elongated sidewalls, but not on the first or second passivation layers. In one embodiment, the dimensions of the patterned features and the film deposition process result in a single crystalline Group-III Nitride film having a third crystal orientation normal to the substrate surface. In another embodiment, the dimensions and orientation of the patterned features and the film deposition process result in a plurality of single crystalline Group-III Nitride films. In other embodiments, additional layers are formed on the Group-III Nitride film or films to form semiconductor devices, for example, a light-emitting diode.

Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.

Abstract: A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

Abstract: The present disclosure relates to a device comprising a mono-crystalline substrate, the mono-crystalline substrate having at least one recessed region which exposes predetermined crystallographic planes of the mono-crystalline substrate, the at least one recessed region further having a recess width and comprising a filling material and an embedded nanochannel, wherein the width, the shape, and the depth of the embedded nanochannel is determined by the recess width of the at least one recessed region and by the growth rate of the growth front of the filling material in a direction perpendicular to the exposed predetermined crystallographic planes. The present disclosure is also related to a method for manufacturing a nanochannel device.

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: Fabrication methods for nano-scale chalcopyritic powders and polymeric thin-film solar cells are presented. The fabrication method for nano-scale chalcopyritic powders includes providing a solution consisting of group IB, IIIA, VIA elements on the chemistry periodic table or combinations thereof. The solution is heated by a microwave generator. The solution is washed and filtered by a washing agent. The solution is subsequently dried, thereby acquiring nano-scale chalcopyritic powders.

Abstract: This invention describes a method of making solar cells wherein the efficiency of the solar cell is enhanced by defining a diffraction grating either on top of the cell or at the bottom of the cell. The diffraction grating spacing is defined such that it bends one or more wavelengths of the incident radiation thereby making those wavelengths traverse in the direction of the plane of the device. The addition of a diffraction grating is done in conjunction with thinning down the cell such that the minority carriers generated (holes and electrons) have a higher probability of being collected. The combined effect of the diffraction grating and the reduced thickness in the solar cell increases the efficiency of the solar cell.

Abstract: Exemplary embodiments provide semiconductor devices with a high-quality semiconductor material on a lattice mismatched substrate and methods for their manufacturing using low temperature growth techniques followed by an insulator-capped annealing process. The semiconductor material can have high-quality with a sufficiently low threading dislocation (TD) density, and can be effectively used for integrated circuit applications such as an integration of optically-active materials (e.g., Group III-V materials) with silicon circuitry. In an exemplary embodiment, the high-quality semiconductor material can include one or more ultra-thin high-quality semiconductor epitaxial layers/films/materials having a desired thickness on the lattice mismatched substrate. Each ultra-thin high-quality semiconductor epitaxial layer can be formed by capping a low-temperature grown initial ultra-thin semiconductor material, annealing the capped initial ultra-thin semiconductor material, and removing the capping layer.

Abstract: A solid state light source includes a substrate having a top surface and a bottom surface, and at least one optically active layer on the top surface of the substrate. At least one of the top surface, the bottom surface, the optically active layer or an emission surface on the optically active layer includes a patterned surface that includes a plurality of tilted surface features that have a high elevation portion and a low elevation portion that define a height (h), and wherein the plurality of tilted surface features define a minimum lateral dimension (r). The plurality of tilted surface features provide at least one surface portion that has a surface tilt angle from 3 to 85 degrees. The patterned surface has a surface roughness <10 nm rms, and h/r is ?0.05.

Abstract: A method of manufacturing a solar cell module, including: forming a laminated body including a first protective member, a first sealing member having a first melting point, a plurality of solar cells, a second sealing member having a second melting point higher than the first melting point, and the second protective member; heating the first sealing member to a temperature equal to or higher than the first melting point but lower than the second melting point; and heating the second sealing member to a temperature equal to or higher than the second melting point. In forming the laminated body, the second sealing member is arranged to form a surface including a plurality of convex portions faces the first sealing member.