Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second regio

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. Similarly, a method for forming thin to ultra-thin strain Si, SiC, or SiC/Si layers directly on insulator substrates having a strain content in the range of about 1-5% is further described.

Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes forming a metal catalytic pattern on a semiconductor substrate; etching the semiconductor substrate using the metal catalytic pattern as an etching mask to form a recess; forming an insulating layer over a structure including the recess, the metal catalytic pattern, and the semiconductor substrate; patterning the insulating layer to cross over the metal catalytic pattern and to expose a predetermined portion of the metal catalytic pattern; and growing a nano wire using the exposed predetermined portion of the metal catalytic pattern.

Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.

Abstract: A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant.

Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.

Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

Abstract: A dielectric film containing Zr—Sn—Ti—O and methods of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Films of Zr—Sn—Ti—O may be formed in a self-limiting growth process.

Abstract: A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or plasma etching of the back side. The thin layer or film of reinforcement material fills grooves, fractures and scratches in the back side of the wafer, enhances the rigidity of the wafer and provides a planar, smooth, back side surface layer. The reinforcement material counteracts internal stresses of the wafer tending to warp, crack and propagate lattice defects in the wafer. The reinforcement material may also be configured to act as a die attach adhesive, may provide an ionic barrier, and may remain as part of the packaging for semiconductor dice singulated from the wafer.

Abstract: Electronic apparatus, systems, and methods include structures having a dielectric layer containing zirconium silicon oxide film. The zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed.

Abstract: Various structures having a dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI4 precursor and a method of fabricating structures having such a dielectric film produce the structures with a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Dielectric films containing Zr—Sn—Ti—O formed by atomic layer deposition using TiI4 are thermodynamically stable such that the Zr—Sn—Ti—O will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.

Abstract: A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the device, germanium atoms are implanted into a surface of a semiconductor substrate such that a germanium-containing layer inside the semiconductor substrate is formed. Then, the surface of the semiconductor surface is oxidized down to and including the upper part of the germanium-containing layer, thereby pushing the implanted germanium atoms from the surface down into the semiconductor substrate and thereby enhancing the germanium concentration inside the remaining germanium-containing layer and forming a layer with enhanced germanium concentration inside the semiconductor substrate. The fabrication of the semiconductor device is concluded such that the active region of the device is placed at least partly within the layer with enhanced germanium concentration.

Abstract: A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Abstract: Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

Abstract: A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Abstract: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxia