Abstract: Reaction vessels which allow visualization while speeding vaporization or other reactions. In one illustrative embodiment, a reaction vessel may have sidewalls formed from a transparent material such as a clear quartz glass having relatively smooth surface and relatively low thermal transfer properties while allowing for visualization into the vessel. The vessel floor may be formed from a porous textured opaque quartz glass bottom. Liquids in the vessel will more readily react due to the numerous pores on the surface of the material of the bottom which serve as active nucleation sites during a chemical reaction process. Additionally, an unexpectedly higher rate of thermal diffusivity into the vessel interior may further increase reaction speeds. Methods of conducting and analyzing reactions using such vessels are further included in the present disclosure.

Abstract: A sample for microstructure diagnostics includes a sample body holder with accommodation structures to accommodate a sample body in a defined accommodation position; and at least one sample body produced separately from the sample body holder, the sample body having at least one solid handling portion and, adjoining the handling portion, a target portion thinner relative to the handling portion, the target portion being delimited at a narrow side by a sample body top side and, laterally, by side faces extending in a perpendicular or oblique manner in relation to the sample body top side, with the sample body being affixed to the accommodation structures in the accommodation position.

Abstract: An improved approach is described to implement an LED-based large area display which uses an array of single color solid state lighting elements (e.g. LEDs). In some embodiments, the panel comprises an array of blue LEDs, where each pixel of the array comprises three blue LEDs. An overlay is placed over the array of blue LEDs, where the overlay comprises a printed array of phosphor portions. Each pixel on the PCB comprised of three blue LEDs is matched to a corresponding portion of the overlay having the printed phosphor portions. The printed phosphor portions of the overlay includes a number of regions of blue light excitable phosphor materials that are configured to convert, by a process of photoluminescence, blue excitation light generated by the light sources into green or red and colored light. Regions of the overlay associated with generating blue light comprise an aperture/window that allows blue light to pass through the overlay.

Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.

Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.

Abstract: Without sacrificial layer etching, a microstructure and a micromachine are manufactured. A separation layer 102 is formed over a substrate 101, and a layer 103 to be a movable electrode is formed over the separation layer 102. At an interface of the separation layer 102, the layer 103 to be a movable electrode is separated from the substrate. A layer 106 to be a fixed electrode is formed over another substrate 105. The layer 103 to be a movable electrode is fixed to the substrate 105 with the spacer layer 103 which is partially provided interposed therebetween, so that the layer 103 to be a movable electrode and a layer 106 to be a fixed electrode face each other.

Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.

Abstract: A method and apparatus to manage the diffusion process by controlling the diffusion path in the semiconductor fabrication process is disclosed. In one embodiment, a method for processing a substrate comprising steps of forming one or more diffusion areas on said substrate; disposing the substrate in a diffusion chamber, wherein the diffusion chamber is under a vacuum condition and a source material therein is heated and evaporated; and diffusing the source material into the diffusion area on said substrate, wherein said source material travels through a diffusion controlling unit adapted to manage the flux thereof in the diffusion chamber, so concentration of the source material is uniform in a diffusion region above the substrate.

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.

Abstract: In a semiconductor die, source zones of a first conductivity type and body zones of a second conductivity type are formed. Both the source and the body zones adjoin a first surface of the semiconductor die in first sections. An impurity source is provided in contact with the first sections of the first surface. The impurity source is tempered so that atoms of a metallic recombination element diffuse out from the impurity source into the semiconductor die. Then impurities of the second conductivity type are introduced into the semiconductor die to form body contact zones between two neighboring source zones, respectively. The atoms of the metallic recombination element reduce the reverse recovery charge in the semiconductor die. Providing the body contact zones after tempering the platinum source provides uniform and reliable body contacts.

Abstract: A method for fabricating a semiconductor device including performing oxygen plasma treatment to a surface of a nitride semiconductor layer, a power density of the oxygen plasma treatment being 0.2 to 0.3 W/cm2.

Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the

Abstract: Proposed is the backside silicon photovoltaic cell and method for forming backside selective emitters, backside doped base contact regions, backside field-induced emitters, FSF-regions, and contacts to the functional regions of a backside solar cell by essentially electrical means and without conventional thermal diffusion and masking processes. The process includes forming conductive layers on both sides of an intermediate device structure, performing Joule heating by passing electrical current through the backside conductive layers thus forming the selective emitters, the base contact regions, and contacts to the functional regions. The obtained structure is then subjected to pulse electrical treatment by applying a voltage pulse or pulses between the front and back conductive layers to form the field-induced emitter and the field-induced FSF. After the conductive layers are removed, a final solar cell is obtained.

Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.

Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film (112), a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.

Abstract: Without sacrificial layer etching, a microstructure and a micromachine are manufactured. A separation layer 102 is formed over a substrate 101, and a layer 103 to be a movable electrode is formed over the separation layer 102. At an interface of the separation layer 102, the layer 103 to be a movable electrode is separated from the substrate. A layer 106 to be a fixed electrode is formed over another substrate 105. The layer 103 to be a movable electrode is fixed to the substrate 105 with the spacer layer 103 which is partially provided interposed therebetween, so that the layer 103 to be a movable electrode and a layer 106 to be a fixed electrode face each other.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Abstract: A method of manufacturing nonvolatile memory devices comprises forming a plurality of floating gates spaced from each other over a semiconductor substrate, forming a dielectric layer on a surface of the floating gates, forming a capping layer on a surface of the dielectric layer, adding impurities to the capping layer, and forming a control gate over the capping layer containing the impurities.

Abstract: An EL display device comprising pixels, each of the pixels comprises an EL element and a TFT, and a counter substrate. The counter substrate is provided with a light shielding film disposed in an area covering at least a space between two pixels and color filters having one of three different colors.

Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.

Abstract: A method for infusing material below the surface of a substrate is described. The method comprises modifying a surface condition of a surface on a substrate to produce a modified surface layer, and thereafter, infusing material into the modified surface in the substrate by exposing the substrate to a gas cluster ion beam (GCIB) comprising the material.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface. The method further includes depositing an ink on the front substrate surface in a ink pattern, the ink comprising a set of silicon-containing particles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified film ink pattern.

Abstract: This sheet production apparatus comprises a vessel defining a channel configured to hold a melt. The melt is configured to flow from a first point to a second point of the channel. A cooling plate is disposed proximate the melt and is configured to form a sheet on the melt. A spillway is disposed at the second point of the channel. This spillway is configured to separate the sheet from the melt.

Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.

Abstract: Method for simultaneously forming doped regions having different conductivity-determining type elements profiles are provided. In one exemplary embodiment, a method comprises the steps of diffusing first conductivity-determining type elements into a first region of a semiconductor material from a first dopant to form a doped first region. Second conductivity-determining type elements are simultaneously diffused into a second region of the semiconductor material from a second dopant to form a doped second region. The first conductivity-determining type elements are of the same conductivity-determining type as the second conductivity-determining type elements. The doped first region has a dopant profile that is different from a dopant profile of the doped second region.

Abstract: A method is described for isotropic or nearly isotropic shallow doping of a non-planar surface exposed in a void. The results of ion implantation, a common doping method, are inherently planar. Some fabrication methods and devices may require doping a surface of a non-planar feature exposed in a void, such as a trench. The feature is doped by flowing a gas which will provide the dopant over the exposed surfaces, or by exposing the surfaces to a plasma including the dopant. The feature may be a patterned feature, including a top surface and a sidewall. In a preferred embodiment, a semiconductor feature having a top surface and a sidewall is exposed in a trench formed in a dielectric, and a gas providing a p-type or n-type dopant is flowed in the trench, providing a p-type or n-type dopant to the semiconductor.

Abstract: Semiconductor structures are disclosed including a substrate comprising a semiconductor material and having opposed first and second surfaces, and at least one conductive via extending from the first surface to the second surface. The conductive vias can extend at angles relative to the first surface, such as acute angles or 90°. The conductive vias can include segments that extend at different angles. Methods of forming conductive vias in semiconductor structures are provided. In the methods, a thermal gradient is applied in combination with an electric field to form conductive vias.

Abstract: A semiconductor device includes a vertically extending semiconductor portion above a semiconductor substrate, first and second diffusion regions being disposed near the bottom and top portions of the vertically extending semiconductor portion, respectively. A gate insulating film extends along the side surface of the vertically extending semiconductor portion which is separated by the gate insulating film from a gate electrode. The level of the top portion of the gate electrode is nearly equal to or lower than the level of the bottom portion of the second diffusion regions and the level of the bottom portion of the gate electrode is nearly equal to or higher than the level of the top portion of the first diffusion region.

Abstract: A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper opening self-aligned to and communicated with the lower opening is formed in the second dielectric layer, wherein the upper opening and the lower opening constitute a self-aligned contact opening. Afterwards, the self-aligned contact opening is filled with a conductive layer.

Abstract: The substrate with electrodes is formed of a transparent material onto which is deposited a film (1) of a transparent conductive material of thickness e1 and of refractive index n1, said film being structured to form a set of electrodes (1a) whose contours (8) delimit insulating spaces (3), wherein the insulating spaces (3) are filled with a transparent dielectric material of thickness e2 and of refractive index n2 so that the respective thicknesses of the conductive material and the dielectric material are inversely proportional to the values of the refractive indices of said materials and said dielectric material forms neither depressions nor beads at the contour (8) of the electrodes. A hardcoating layer (7) may be disposed between the substrate (5) and the electrodes and a protective film (9) added. The substrate with electrodes is obtained by UV irradiation through a single mask.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a VxNy layer and a VxNyOz layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Abstract: A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

Abstract: A method for manufacturing a semiconductor device includes: the first step of forming, in an insulating film provided on a substrate, a recess that is porositized at least at inner walls; the second step of forming an alloy layer made of copper and a metal other than copper so as to cover the inner walls of the recess; the third step of burying a conductive layer made primarily of copper in the recess provided with the alloy layer; the fourth step of subjecting the thus treated substrate to thermal treatment to cause the metal in the alloy layer to react with a constituent component of the insulating film to form a barrier film made of a metal compound having Cu diffusion barrier properties.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a VxNy layer and a VxNyOz layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the position corresponding to periphery of each pixel (102), while a color filter (113) is disposed at the position corresponding to each of the pixels (102). This light shielding film makes the contour of the pixels clear, resulting in an image display with high definition. In addition, it is possible to fabricate the EL display device of the present invention with most of an existing manufacturing line for liquid crystal display devices. Thus, an amount of equipment investment can be significantly reduced, thereby resulting in a reduction in the total manufacturing cost.

Abstract: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.

Abstract: A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Abstract: A method of connecting stranded wire to a lead-frame body 10 includes the provision of a stranded wire 12. It is ensured that insulation is stripped from an end 14 of the stranded wire. An electrically conductive lead-frame connection structure 16 is associated with the lead-frame body. The end 14 of the stranded wire is inserted into the lead-frame connection structure 16 so that the lead-frame connection structure substantially surrounds the wire end. Solder flux is injected so as to be substantially about a portion of the end of the stranded wire. The lead-frame connection structure is placed in contact with a bottom resistance welding electrode 18 or a top resistance welding electrode 20.

Abstract: A dopant diffusion method includes: diffusing a dopant element into a semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr. A temperature of the semiconductor is set less than 750° C. and not more than 950° C. A method of manufacturing a semiconductor device including a semiconductor with a dopant element diffused therein, the method includes: diffusing a dopant element into the semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr, and a temperature of the semiconductor is set less than 750° C. and not more than 950° C.

Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.

Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

Abstract: A process for forming and/or modifying dielectric films on semiconductor substrates is disclosed. According to the present invention, a semiconductor wafer is exposed to a process gas containing a reactive component. The temperature to which the semiconductor wafer is heated and the partial pressure of the reactive component are selected so that, sometime during the process, diffusion of the reactive components occurs through the dielectric film to the film/semiconductor substrate interface. Further, diffusion also occurs of semiconductor atoms through the dielectric film to an exterior surface of the film. The process of the present invention has been found well suited to forming and/or modifying very thin dielectric films, such as films having a thickness of less than 8 nm.