From Or Into Plasma Phase (epo) Patents (Class 257/E21.143)
  • Patent number: 10461198
    Abstract: Disclosed is a thin film transistor substrate that may include a base substrate, a first protection film disposed on the base substrate, an oxide semiconductor layer disposed on the first protection film, a gate electrode insulated from the oxide semiconductor layer and partially overlapped with at least one portion of the oxide semiconductor layer, a source electrode connected with the oxide semiconductor layer, and a drain electrode provided at a predetermined interval from the source electrode and connected with the oxide semiconductor layer, wherein the oxide semiconductor layer has a hydrogen content of 2.4 at % (atomic % or atom %)˜2.6 at %.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 29, 2019
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Jin Seong Park, Kyung Chul Ock, Ki Lim Han, JongUk Bae, SeungMin Lee, JuHeyuck Baeck
  • Patent number: 10355004
    Abstract: A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Sangwoo Pae, Hagju Cho
  • Patent number: 9893153
    Abstract: A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, a first region provided between the SiC layer and the gate insulating film, and a second region provided in the SiC layer. The first region contains at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine). The second region provided adjacent to the first region, and the second region has a higher oxygen concentration than a concentration of the at least one element.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 9865455
    Abstract: Provided are methods and apparatuses for depositing a nitride film using one or more plasma-enhanced atomic layer deposition cycles and one or more thermal atomic layer deposition cycles in a single reactor. The number of thermal atomic layer deposition cycles can be equal to or greater than the number of plasma-enhanced atomic layer deposition cycles. Incorporation of thermal atomic layer deposition cycles with plasma-enhanced atomic layer deposition cycles can allow for greater fine-tuning of properties of the nitride film. In some implementations, the nitride film is a silicon nitride film. The silicon nitride film can be fine-tuned to allow for a more silicon-rich film with a greater refractive index. In some implementations, the plasma-enhanced atomic layer deposition cycles and the thermal atomic layer deposition cycles can be maintained at the same wafer temperature.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 9, 2018
    Assignee: Lam Research Corporation
    Inventors: James Samuel Sims, Kathryn Merced Kelchner
  • Patent number: 9842877
    Abstract: A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: December 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Keiichi Itagaki
  • Patent number: 9716157
    Abstract: A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region. A silicon-containing material is formed on the second region. A first silicon dioxide region is formed on the first region. A second silicon dioxide region is formed by oxidizing the silicon-containing material. A gate runner is electrically connected to a gate electrode and formed in a position facing the second silicon dioxide region. Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 25, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Yu Saitoh
  • Patent number: 9704712
    Abstract: According to various embodiments, a method may include: structuring a semiconductor region to form a structured surface of the semiconductor region; disposing a dopant in the semiconductor region; and activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 11, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Breymesser, Stephan Voss
  • Patent number: 9704602
    Abstract: A random number generation circuit may include a memory block. The random number generation circuit may include a fuse block configured to store an address of a failed memory cell from a memory cell array of the memory block, as a repair address, and generate a match signal by comparing the repair address with a normal address inputted from an exterior. The random number generation circuit may include a register configured to output a true random number by latching an address corresponding to activation timing of the match signal among normal addresses.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 11, 2017
    Assignee: SK hynix Inc.
    Inventors: Kyung Hoon Kim, In Sik Yoon
  • Patent number: 9595444
    Abstract: A method of forming a NAND flash memory includes anisotropically etching trenches of a gate stack down to an intermediate level in a floating gate polysilicon layer, leaving remaining portions of the floating gate polysilicon over the gate dielectric layer. Subsequently, forming a protective layer along exposed sides of the trenches. Then, electrically separating individual floating gates by a selective process that is directed to the remaining portions of the floating gate polysilicon layer exposed by trenches.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: March 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Toshiya Yokota, Atsushi Shimoda, Takuya Sakurai
  • Patent number: 9490361
    Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle ? preferably about ?90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Stefan Flachowsky, Thilo Scheiper
  • Patent number: 9355899
    Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: May 31, 2016
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong Ho Lee, Kyung Do Kim
  • Patent number: 9023693
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Patent number: 8785286
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Patent number: 8748240
    Abstract: Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8735900
    Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mayumi Mizutami, Toshimitsu Konuma
  • Patent number: 8697552
    Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 15, 2014
    Assignee: Intevac, Inc.
    Inventors: Babak Adibi, Moon Chun
  • Patent number: 8680524
    Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chi-sung Oh
  • Patent number: 8536051
    Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hikaru Ohira, Tomoyuki Kirimura
  • Patent number: 8524619
    Abstract: A method for fabricating a semiconductor device including performing oxygen plasma treatment to a surface of a nitride semiconductor layer, a power density of the oxygen plasma treatment being 0.2 to 0.3 W/cm2.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 8513134
    Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Omura, Yumi Ohno, Takaya Matsushita, Tokuhisa Ohiwa
  • Patent number: 8501631
    Abstract: A method for controlling a plasma processing system using wafer bias information derived from RF voltage information is proposed. The RF voltage is processed via an analog or digital methodology to obtain peak voltage information at least for each of the fundamental frequencies and the broadband frequency. The peak voltage information is then employed to derive the wafer bias information to serve as a feedback or control signal to hardware/software of the plasma processing system.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: August 6, 2013
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Henry S. Povolny
  • Patent number: 8450745
    Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mayumi Mizukami, Toshimitsu Konuma
  • Patent number: 8431468
    Abstract: An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 30, 2013
    Assignee: Infineon Technologies AG
    Inventor: Domagoj Siprak
  • Patent number: 8421076
    Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20130078789
    Abstract: A substrate processing apparatus includes a process chamber accommodating a substrate including a thin film formed at a film-forming temperature; a gas supply unit for supplying a process gas including oxygen and/or nitrogen onto the substrate; an excitation unit for exciting the process gas supplied into the process chamber; a heating unit for heating the substrate; an exhaust unit for exhausting an inside of the process chamber; and a control unit for controlling the gas supply unit, the excitation unit, the heating unit and the exhaust unit such that a temperature of the substrate is equal to or lower than the film-forming temperature when the substrate is processed by heating the substrate by the heating unit, exciting the process gas supplied from the gas supply unit by the excitation unit, and supplying the process gas excited by the excitation unit onto a surface of the substrate.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 28, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Hitachi Kokusai Electric Inc.
  • Patent number: 8404573
    Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Satoshi Maeshima, Ichiro Nakayama, Bunji Mizuno
  • Publication number: 20130072006
    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.
    Type: Application
    Filed: November 12, 2012
    Publication date: March 21, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Micron Technology, Inc.
  • Patent number: 8288259
    Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Patent number: 8216922
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Patent number: 8207046
    Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: June 26, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Shin Matsumoto, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20120135586
    Abstract: A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current.
    Type: Application
    Filed: July 20, 2011
    Publication date: May 31, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Seung Hwan KIM
  • Publication number: 20120129325
    Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: INTEVAC, INC.
    Inventors: Babak Adibi, Moon Chun
  • Patent number: 8183571
    Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film (112), a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 22, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mayumi Mizukami, Toshimitsu Konuma
  • Publication number: 20120115317
    Abstract: In a plasma torch unit, a conductor rod having a spiral shape is disposed inside a quartz pipe having a surface coated with boron glass, and a brass block is disposed on the periphery thereof. While a gas is being supplied into a cylindrical chamber, a high-frequency power is supplied to the conductor rod and a plasma is generated in the cylindrical chamber, so that a base material is irradiated with the plasma.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 10, 2012
    Inventors: Tomohiro OKUMURA, Mitsuo Saitoh, Ichiro Nakayama, Taro Kitaoka
  • Patent number: 8124507
    Abstract: A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: February 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Publication number: 20120015507
    Abstract: A plasma doping apparatus for adding an impurity to a semiconductor substrate includes a chamber, a gas supply unit configured for supplying gas to the chamber, and a plasma source by which to cause the chamber to generate plasma of the supplied gas. The mixed gas containing material gas containing an impurity element to be added to the semiconductor substrate, hydrogen gas, and diluent gas for diluting the material gas is supplied to the chamber.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 19, 2012
    Applicants: SEN CORPORATION, SUMITOMO HEAVY INDUSTRIES, LTD.
    Inventors: Masaru Tanaka, Masashi Kuriyama, Hiroki Murooka
  • Publication number: 20110275201
    Abstract: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1? of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2? of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 10, 2011
    Applicant: Panasonic Corporation
    Inventors: Yuichiro SASAKI, Keiichi Nakamoto, Katsumi Okashita, Hisataka Kanada, Bunji Mizuno
  • Patent number: 7981779
    Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Cheng-Guo Jin, Bunji Mizuno
  • Publication number: 20110147856
    Abstract: A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 23, 2011
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Patent number: 7955911
    Abstract: A thin film transistor liquid crystal display (TFT-LCD) pixel unit and a method for manufacturing the same. The pixel unit comprises a gate line and a gate electrode formed on a substrate and a first gate insulating layer, an active layer, and a doped layer that are sequentially formed on the gate line and the gate electrode. An intercepting trench is formed on the gate line to cut off the doped layer and the active layer on the gate line. A second insulating layer covers the intercepting trench and the substrate where the gate line and the gate electrode are not formed. A pixel electrode is formed on the second insulating layer and a part of the pixel electrode overlaps one of a source and drain electrodes.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: June 7, 2011
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Haijun Qiu, Zhangtao Wang, Tae Yup Min, Xu Chen
  • Patent number: 7952103
    Abstract: An EL display device comprising pixels, each of the pixels comprises an EL element and a TFT, and a counter substrate. The counter substrate is provided with a light shielding film disposed in an area covering at least a space between two pixels and color filters having one of three different colors.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: May 31, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mayumi Mizukami, Toshimitsu Konuma
  • Patent number: 7947531
    Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: May 24, 2011
    Assignee: Intermolecular, Inc.
    Inventor: Tony Chiang
  • Patent number: 7923353
    Abstract: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Okmetic Oyj
    Inventor: Jari Mäkinen
  • Publication number: 20110081787
    Abstract: With evacuation of interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to the substrate surface.
    Type: Application
    Filed: November 19, 2010
    Publication date: April 7, 2011
    Inventors: Tomohiro OKUMURA, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Patent number: 7919775
    Abstract: A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: April 5, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Huffman, James N. Hall
  • Patent number: 7910497
    Abstract: Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Tejal Goyani, Johanes Swenberg
  • Publication number: 20110020997
    Abstract: An integrated circuit and method of making it, includes a semiconductor substrate and a support layer disposed on the semiconductor substrate. A gate insulator including a support layer doped using a noise-reducing dopant can be disposed on the semiconductor substrate. A gate stack can be disposed on the gate insulator.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Applicant: Infineon Technologies AG
    Inventor: Domagoj Siprak
  • Patent number: 7864257
    Abstract: A thin film transistor and a method of manufacturing the thin film transistor is disclosed. The thin film transistor includes first and second ohmic contact layers, an activation layer, an insulating layer, a source electrode formed on the insulating layer and connected to the first ohmic contact layer through first contact hole, a drain electrode formed on the insulating layer and connected to the second ohmic contact layer through second contact hole, a gate electrode formed on the insulating layer between the source electrode and the drain electrode and overlapping the activation layer, and a protective layer formed on the source electrode, the drain electrode, and the gate electrode.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: January 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Moo Huh, Joon-Hoo Choi, Seung-Kyu Park
  • Patent number: 7858537
    Abstract: With evacuation of interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to the substrate surface.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Satoshi Maeshima, Bunji Mizuno, Yuichiro Sasaki
  • Patent number: 7846823
    Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: December 7, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yasushi Funakoshi