Abstract: A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

Abstract: A method of multi-step plasma doping a substrate includes igniting a plasma from a process gas. A first plasma condition is established for performing a first plasma doping step. The substrate is biased so that ions in the plasma having the first plasma condition impact a surface of the substrate thereby exposing the substrate to a first dose. The first plasma condition transitions to a second plasma condition. The substrate is biased so that ions in the plasma having the second plasma condition impact the surface of the substrate thereby exposing the substrate to a second dose. The first and second plasma conditions are chosen so that the first and second doses combine to achieve a predetermined distribution of dose across at least a portion of the substrate.

Abstract: A method is described for isotropic or nearly isotropic shallow doping of a non-planar surface exposed in a void. The results of ion implantation, a common doping method, are inherently planar. Some fabrication methods and devices may require doping a surface of a non-planar feature exposed in a void, such as a trench. The feature is doped by flowing a gas which will provide the dopant over the exposed surfaces, or by exposing the surfaces to a plasma including the dopant. The feature may be a patterned feature, including a top surface and a sidewall. In a preferred embodiment, a semiconductor feature having a top surface and a sidewall is exposed in a trench formed in a dielectric, and a gas providing a p-type or n-type dopant is flowed in the trench, providing a p-type or n-type dopant to the semiconductor.

Abstract: A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.

Abstract: In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) pixel structure comprising: a gate line and a gate electrode formed on a substrate; a first insulating layer, a semiconductor layer, and a doped semiconductor layer formed sequentially on the gate electrode and the gate line, wherein an isolating groove is formed above the gate line which disconnects the semiconductor layer on the gate line; a second insulating layer covering the isolating groove and a portion of the substrate where the gate line and the gate are not formed; a pixel electrode formed on the second insulating layer, wherein the pixel electrode is integral with a drain electrode and is connected with the doped semiconductor layer on the gate electrode at a place where the drain electrode is formed; a source electrode, which is a portion of a data line, formed on the doped semiconductor layer; and a channel formed between the source electrode and the drain electrode.

Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.

Abstract: A change of a beam current of an ion beam which passes an outside of the side of a forestage beam restricting shutter, and which is incident on a forestage multipoints Faraday is measured while the forestage beam restricting shutter is driven in a y direction by a forestage shutter driving apparatus in order to obtain a beam current density distribution in the y direction of the ion beam at a position of the forestage beam restricting shutter. A change of a beam current of the ion beam which passes an outside of the side of a poststage beam restricting shutter, and which is incident on a poststage multipoints Faraday is measured while the poststage beam restricting shutter is driven in the y direction by a poststage shutter driving apparatus in order to obtain a beam current density distribution in the y direction of the ion beam at a position of the poststage beam restricting shutter.

Abstract: A method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. Predetermined gas is exhausted via an exhaust port by a turbo-molecular pump while introducing the gas within the vacuum chamber from a gas supply device, and the pressure within the vacuum chamber is kept at a predetermined value by a pressure regulating valve. A high-frequency power supply for a plasma source supplies a high-frequency power to a coil provided near a dielectric window to generate inductively coupled plasma within the vacuum chamber. A high-frequency power supply for the sample electrode for supplying the high-frequency power to the sample electrode is provided. A matching circuit for the sample electrode and a high-frequency sensor are provided between the sample electrode high-frequency power supply and the sample electrode. An ion current applied to the surface of a sample can be accurately monitored buy using the high-frequency sensor and an arithmetic device.

Abstract: A method for the selective removal of a high-k layer such as HfO2 over silicon or silicon dioxide is provided. More specifically, a method for etching high-k selectively over silicon and silicon dioxide and a plasma composition for performing the selective etch process is provided. Using a BCl3 plasma with well defined concentrations of nitrogen makes it possible to etch high-k with at a reasonable etch rate while silicon and silicon dioxide have an etch rate of almost zero. The BCl3 comprising plasmas have preferred additions of 10 up to 13% nitrogen. Adding a well defined concentration of nitrogen to the BCl3/N2 plasma gives the unexpected deposition of a Boron-Nitrogen (BxNy) comprising film onto the silicon and silicon dioxide which is not deposited onto the high-k material. Due to the deposition of the Boron-Nitrogen (BxNy) comprising film, the etch rate of silicon and silicon dioxide is dropped down to zero.

Abstract: A method for fabricating a semiconductor device comprises forming a channel of a transistor, wherein the channel has a first conductivity type. The method further comprises depositing a layer of dielectric on at least a portion of the channel. The method further comprises etching a notch in the layer of dielectric wherein at least a portion of the notch is etched at least to the channel. The method also comprises doping the portion of the channel in the notch with material of a second conductivity type. The method further comprises filling the notch with polysilicon.

Abstract: A semiconductor manufacturing apparatus and method are disclosed in which the apparatus comprises a reaction tube configured to hold one or more wafers, a spray pipe coupled to the reaction tube for spraying reaction gas into the reaction tube, and a plurality of electrodes used to convert the reaction gas to a plasma state. The electrodes include a cathode and an anode plasma electrode arranged for exciting reaction gas exiting the spray pipe to a plasma state prior to entry into the reaction tube. A switching device is coupled to both the cathode and anode plasma electrode and configured to switch a polarity of a high voltage applied to each of the cathode and anode to prevent a build-up of positive plasma reaction gas ions on the cathode during repeated processing steps.

Abstract: A method of introducing an impurity and an apparatus for introducing the impurity forms an impurity layer easily in a shallower profile. Component devices manufactured taking advantage of these method or apparatus are also disclosed. When introducing a material to a solid substance which has an oxidized film or other film sticking at the surface, the present method and apparatus first removes the oxidized film and other film using at least one means selected from among the group consisting of a means for irradiating the surface of solid substance with plasma, a means for irradiating the surface of solid substance with gas and a means for dipping the surface of solid substance in a reductive liquid; and then, attaches or introduces a certain desired particle. The way of attaching, or introducing, a particle is bringing a particle-containing gas to make contact to the surface, which surface has been made to be free of the oxidized film and other film.

Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.

Abstract: In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.

Abstract: Methods and apparatus are provided for igniting, modulating, and sustaining a plasma for various doping processes. In one embodiment, a substrate (250) can be doped by forming a plasma (610) in a cavity (285) by subjecting a gas to an amount of electromagnetic radiation in the presence of a plasma catalyst (240) and adding at least one dopant material to the plasma. The material is then allowed to penetrate into the substrate. Various active and passive catalysts are provided.

Abstract: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: Ion sources and methods for generating molecular ions in a cold operating mode and for generating atomic ions in a hot operating mode are provided. In some embodiments, first and second electron sources are located at opposite ends of an arc chamber. The first electron source is energized in the cold operating mode, and the second electron source is energized in the hot operating mode. In other embodiments, electrons are directed through a hole in a cathode in the cold operating mode and are directed at the cathode in the hot operating mode. In further embodiments, an ion beam generator includes a molecular ion source, an atomic ion source and a switching element to select the output of one of the ion sources.

Abstract: A high quality bonded substrate is obtained in which generation of microprotrusions and cracked particles are restricted on a surface of an active layer of the bonded substrate and the surface of the active layer is flattened. A laminated body is formed by overlapping a first semiconductor substrate serving as an active layer onto a second semiconductor substrate serving as a support substrate via an oxide film or without an oxide film; the active layer is formed by forming a thin film from the first semiconductor substrate; and the surface of the active layer is flattened by vapor-phase etching. After forming a thin film from the first semiconductor substrate and before flattening the surface of the active layer by the vapor-phase etching, an organic substance adhering to the surface of the active layer is removed and a native oxide film generated on the surface of the active layer is removed after removing the organic substance.

Abstract: A method of producing a semiconductor device includes the steps of: introducing a p-type impurity corresponding to a conductive type of a channel area into a channel forming area; introducing fluorine into the channel forming area at a low acceleration voltage; and thermally processing a substrate to increase a threshold voltage. In the method of the present invention, the step of thermally processing the substrate is performed after the steps of introducing the p-type impurity into the channel forming area and introducing fluorine into the channel forming area. Further, the steps of introducing the p-type impurity into the channel forming area and introducing fluorine into the channel forming area may be performed any order.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.

Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.

Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.

Abstract: Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Abstract: A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpiece and the ceiling, and introducing into the chamber a process gas which includes the species to be implanted in the surface layer of the workpiece. The method further includes generating from the process gas a plasma by inductively coupling RF source power into the processing zone from an RF source power generator through an inductively coupled RF power applicator, and applying an RF bias from an RF bias generator to the workpiece support.

Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: With evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: A method of fabricating a thin film transistor for liquid crystal display is provided. A polysilicon island and a gate insulating layer covered on the polysilicon island are formed on a substrate. A metal layer is formed on the gate insulating layer. A pair of trenches exposing predetermined regions of the polysilicon island are formed in the metal layer and the gate insulating layer. P-type impurities are doped into the uncovered polysilicon regions of the polysilicon island. A gate electrode is formed by removing parts of the metal layer and the gate insulating layer. N-type impurities are doped into the exposed portions of the polysilicon island. Thereby LDD regions, and a source and a drain regions are formed at the regions doped with both n-type and p-type impurities and at the regions doped with only n-type impurities respectively.