Using Predeposition Of Impurities Into The Semiconductor Surface, E.g., From Gaseous Phase (epo) Patents (Class 257/E21.146)
  • Patent number: 9917181
    Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Frank Dieter Pfirsch, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Stephan Voss
  • Patent number: 8440578
    Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 14, 2013
    Assignee: TEL Epion Inc.
    Inventor: John Gumpher
  • Patent number: 7754605
    Abstract: The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 13, 2010
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Steven J Radigan
  • Publication number: 20080318399
    Abstract: A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which repeatability of an apparatus control can be secured. The invention has been finalized focusing on the result. That is, if plasma irradiation starts, a dose is initially increased, but a time at which the dose is made substantially uniform without depending on a time variation is continued. In addition, if the time is further increased, the dose is decreased. The dose can be accurately controlled through a process window of the time at which the dose is made substantially uniform without depending on the time variation.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 25, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuichiro SASAKI, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno, Tomohiro Okumura
  • Publication number: 20080142931
    Abstract: An impurity region having a box-shaped impurity profile is formed. An impurity introducing method includes a step of introducing a desired impurity into a surface of a solid base body, and a step of radiating plasma to a surface of the solid base body after the impurity introducing step thus forming an impurity profile having an approximately box-shape.
    Type: Application
    Filed: March 17, 2005
    Publication date: June 19, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuichiro Sasaki, Ichiro Nakayama, Bunji Mizuno
  • Patent number: 7303967
    Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hoon Sa
  • Patent number: 7214618
    Abstract: A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Weimin Li, Sam Yang