Using Diffusion Into Or Out Of A S Olid From Or Into A Solid Phase, E.g., A Doped Oxide Layer (epo) Patents (Class 257/E21.144)
  • Patent number: 9812559
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Bong-Soo Kim, Hyun-Seung Kim, Hyun-Gi Hong
  • Patent number: 9761584
    Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • Patent number: 8980719
    Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yu-Lien Huang, De-Wei Yu
  • Patent number: 8956961
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Rexchip Electronics Corporation
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Patent number: 8912083
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 16, 2014
    Assignee: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Patent number: 8841733
    Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Fu Huang, Kun-Hsien Lin, Chi-Mao Hsu, Min-Chuan Tsai, Tzung-Ying Lee, Chin-Fu Lin
  • Patent number: 8703593
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Publication number: 20140094025
    Abstract: A method for processing a semiconductor assembly is presented. The method includes: (a) contacting at least a portion of a semiconductor assembly with a chalcogen source, wherein the semiconductor assembly comprises a semiconductor layer comprising a semiconductor material disposed on a support; (b) introducing a chalcogen from the chalcogen source into at least a portion of the semiconductor material; and (c) disposing a window layer on the semiconductor layer after the step (b).
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Bastiaan Arie Korevaar, Faisal Razi Ahmad
  • Publication number: 20140042593
    Abstract: A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Reinhard Ploss, Hans-Joachim Schulze
  • Publication number: 20140001514
    Abstract: A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm?3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm?3.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
  • Publication number: 20130280883
    Abstract: Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Juergen Faul, Frank Jakubowski
  • Patent number: 8536004
    Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 17, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Yi-Lin Sun
  • Patent number: 8536003
    Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 17, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Yi-Lin Sun
  • Publication number: 20130234230
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20130122676
    Abstract: The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventor: Pei-Ren Jeng
  • Publication number: 20130102137
    Abstract: The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventor: Pei-Ren Jeng
  • Patent number: 8415239
    Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: April 9, 2013
    Assignee: ABB Technology AG
    Inventors: Jan Vobecky, Munaf Rahimo
  • Publication number: 20130061922
    Abstract: A diffusion agent composition used in forming an impurity diffusion agent layer on a semiconductor substrate, and containing an impurity diffusion component, a silicon compound, and a solvent containing a solvent having a boiling point of 100° C. or less, a solvent having a boiling point of 120-180° C., and a solvent having a boiling point of 300° C.
    Type: Application
    Filed: April 12, 2011
    Publication date: March 14, 2013
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Atsushi Murota, Takaaki Hirai
  • Patent number: 8394710
    Abstract: A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20130040447
    Abstract: Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.
    Type: Application
    Filed: September 7, 2012
    Publication date: February 14, 2013
    Inventors: Shankar Swaminathan, Mandyam Sriram, Bart van Schravendijk, Pramod Subramonium, Adrien La Voie
  • Patent number: 8367533
    Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Yun, Gil-heyun Choi, Jong-Myeong Lee
  • Patent number: 8309446
    Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. In one embodiment, the methods include forming a doping layer on a back surface of a substrate, heating the doping layer and substrate to cause the doping layer diffuse into the back surface of the substrate, texturing a front surface of the substrate after heating the doping layer and the substrate, forming a dielectric layer on the back surface of the substrate, removing portions of the dielectric layer from the back surface to from a plurality of exposed regions of the substrate, and depositing a metal layer over the back surface of the substrate, wherein the metal layer is in electrical communication with at least one of the plurality of exposed regions on the substrate, and at least one of the exposed regions has dopant atoms provided from the doping layer.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: November 13, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weidman, Rohit Mishra, Michael P. Stewart, Yonghwa Chris Cha, Kapila P. Wijekoon, Hongbin Fang
  • Patent number: 8236675
    Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 7, 2012
    Assignee: SemEquip, Inc.
    Inventors: Wade A. Krull, Dale C. Jacobson
  • Publication number: 20120184062
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 19, 2012
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Takuya Aoyagi
  • Patent number: 8222131
    Abstract: Provided is a method of forming an image sensor. The method may include providing a single crystalline semiconductor layer including at least one photodiode onto a support substrate; forming a material layer including dopants on the single crystalline semiconductor layer; and forming a dopant diffusion layer in the single crystalline semiconductor layer by diffusing the dopants of the material layer.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi Bum Kim, Yun Ki Lee
  • Patent number: 8216940
    Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: July 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Motoyama
  • Publication number: 20120160306
    Abstract: A diffusion agent composition including an impurity-diffusing component (A); a binder resin (B) that thermally decomposes and disappears below a temperature at which the impurity-diffusing component (A) begins to thermally diffuse; SiO2 fine particles (C); and an organic solvent (D) that contains an organic solvent (D1) having a boiling point of at least 100° C.
    Type: Application
    Filed: August 18, 2010
    Publication date: June 28, 2012
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takaaki Hirai, Atsushi Murota, Katsuya Tanitsu
  • Publication number: 20120153438
    Abstract: Certain embodiments combine the use of two or more noble metal impurities (e.g., gold, platinum, palladium, iridium, etc.) to suppress the lifetime of power semiconductors such as diodes. The noble metals may be applied using various methods including, for example, the application of thin films from a liquid suspension of the noble metals (e.g., gold and platinum) and/or alloys thereof onto the wafer and/or the coating the wafer with a layer of the noble metals (e.g., gold and platinum) from high vacuum metal deposition by electron beam or sputtering. The application and drive of the impurities may be simultaneous or sequential.
    Type: Application
    Filed: June 27, 2011
    Publication date: June 21, 2012
    Applicant: SOLID STATE DEVICES, INC.
    Inventor: Allan Harrison
  • Patent number: 8163639
    Abstract: A method of fabricating a photo diode includes sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a semiconductor substrate; forming a doped oxide film, including impurities of the second conductivity type, on the second epitaxial layer; forming a silicon nitride film on the oxide film; and patterning the oxide film and the silicon nitride film to sequentially form an oxide film pattern of the second conductivity type and a silicon nitride film pattern, respectively. The second conductivity type impurities are diffused from the oxide film pattern into the second epitaxial layer using a heat diffusion process to form a doped shallow junction layer of the second conductivity type, which converts the oxide film pattern into a non-conductive oxide film pattern.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kye-wong Maeng, Sung-ryoul Bae
  • Publication number: 20120094427
    Abstract: A method for manufacturing a solar cell comprises disposing a first doping layer on a substrate, forming a first doping layer pattern by patterning the first doping layer to expose a portion of the substrate, disposing a second doping layer on the first doping layer pattern to cover the exposed portion of the substrate, diffusing an impurity from the first doping layer pattern which forms a first doping region in a surface of the substrate, and diffusing an impurity from the second doping layer which forms a second doping region in the surface of the substrate, wherein the forming of the first doping layer pattern uses an etching paste.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 19, 2012
    Inventors: Young Su Kim, Sang Ho Kim
  • Publication number: 20120094426
    Abstract: A method for manufacturing a solar cell comprises disposing a first doping layer on a substrate, forming a first doping layer pattern by patterning the first doping layer to expose a portion of the substrate, disposing a second doping layer on the first doping layer pattern to cover the exposed portion of the substrate, diffusing an impurity from the first doping layer pattern which forms a first doping region in a surface of the substrate, and diffusing an impurity from the second doping layer which forms a second doping region in the surface of the substrate, wherein the forming of the first doping layer pattern uses an etching paste.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 19, 2012
    Inventors: Young Su Kim, Sang Ho Kim
  • Publication number: 20120070971
    Abstract: There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Sai Hooi YEONG, Tao WANG, Shesh Mani Pandey, Chia Ching YEO, Ying Keung LEUNG, Elgin Kiok Boone QUEK
  • Publication number: 20120052618
    Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Inventor: Daniel Inns
  • Publication number: 20120028454
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Application
    Filed: September 23, 2011
    Publication date: February 2, 2012
    Inventors: Shankar Swaminathan, Jon Henri, Dennis M. Hausmann, Pramod Subramonium, Mandyam Sriram, Vishwanathan Rangarajan, Kirthi K. Kattige, Bart J. van Schravendijk, Andrew J. McKerrow
  • Publication number: 20110312168
    Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitabh Jain
  • Publication number: 20110278702
    Abstract: A method for producing a dopant profile is provided. The method includes starting from a surface of a wafer-shaped semiconductor component by introducing dopant atoms into the semiconductor component. The dopant-containing layer is produced on or in a region of the surface in order to produce a provisional first dopant profile and then a plurality of semiconductor components having a corresponding layer is subjected to heat treatment on top of one another in the form of a stack in order to produce a second dopant profile having a greater depth in comparison to the first dopant profile.
    Type: Application
    Filed: December 3, 2009
    Publication date: November 17, 2011
    Inventors: Joerg Horzel, Dieter Franke, Gabriele Blendin, Marco Faber, Wilfried Schmidt
  • Publication number: 20110269287
    Abstract: An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung TSAI, Yu-Lien HUANG, De-Wei YU
  • Patent number: 8035196
    Abstract: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 11, 2011
    Assignee: Zarlink Semiconductor (US) Inc.
    Inventors: Thomas J. Krutsick, Christopher J. Speyer
  • Publication number: 20110237058
    Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 29, 2011
    Inventors: Jung-Ho Yun, Gil-heyun Choi, Jong-Myeong Lee
  • Publication number: 20110223751
    Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon B. Farmer, Lidija Sekaric
  • Publication number: 20110195540
    Abstract: The composition for forming a p-type diffusion layer in accordance with the present invention contains an acceptor element-containing glass powder and a dispersion medium. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 11, 2011
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi
  • Patent number: 7989293
    Abstract: A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 2, 2011
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jun Zeng
  • Publication number: 20110183504
    Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a substrate doped with boron atoms, the substrate comprising a front substrate surface. The method also includes depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents; and heating the substrate in a baking ambient at a baking temperature and for a baking time period wherein a densified ink layer is formed. The method further includes exposing the substrate to a phosphorous dopant source at a drive-in temperature and for a drive-in time period.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Inventors: Giuseppe Scardera, Malcolm Abbott, Dmitry Poplavskyy, Sunil Shah
  • Patent number: 7892976
    Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Motoyama
  • Patent number: 7846823
    Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: December 7, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yasushi Funakoshi
  • Patent number: 7781288
    Abstract: A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Haensch, Steven Koester, Amlan Majumdar
  • Publication number: 20100022077
    Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 28, 2010
    Inventors: Wade A. Krull, Dale C. Jacobson
  • Publication number: 20100003812
    Abstract: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Applicant: Palo Alto Research Center Incorporated
    Inventor: Craig Eldershaw
  • Publication number: 20090269913
    Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 29, 2009
    Inventors: Mason Terry, Homer Antoniadis, Dmitry Poplavskyy, Maxim Kelman
  • Publication number: 20090239363
    Abstract: Methods for forming doped regions in semiconductor substrates using non-contact printing processes and dopant-comprising inks for forming such doped regions using non-contact printing processes are provided. In an exemplary embodiment, a method for forming doped regions in a semiconductor substrate is provided. The method comprises providing an ink comprising a conductivity-determining type dopant, applying the ink to the semiconductor substrate using a non-contact printing process, and subjecting the semiconductor substrate to a thermal treatment such that the conductivity-determining type dopant diffuses into the semiconductor substrate.
    Type: Application
    Filed: November 19, 2008
    Publication date: September 24, 2009
    Applicant: HONEYWELL INTERNATIONAL, INC.
    Inventors: Roger Yu-Kwan Leung, De-Ling Zhou, Wenya Fan