Using An External Electrical Current, I.e., Electro-deposition (epo) Patents (Class 257/E21.175)
  • Patent number: 10950519
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 10757820
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 25, 2020
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 10749278
    Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-Nan Nian, Jyun-Ru Wu, Shiu-Ko Jangjian, Yu-Ren Peng, Chi-Cheng Hung, Yu-Sheng Wang
  • Patent number: 10636758
    Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 10629525
    Abstract: Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Ramanan V. Chebiam, Christopher J. Jezewski, Tejaswi K. Indukuri, James S. Clarke, John J. Plombon
  • Patent number: 10566271
    Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 18, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 10301735
    Abstract: A method of forming a metal coating includes: disposing a solid electrolyte membrane (13) between an anode (11) and a substrate (B) which forms a cathode; bringing a solution (L) containing metal ions into contact with an anode-side portion of the solid electrolyte membrane (13); and causing, in a state where the solid electrolyte membrane (13) is in contact with the substrate (B), a current to flow from the anode (11) to the cathode so as to form a metal coating formed of the metal on the surface of the substrate (B). The metal coating is formed by repeating a current-flowing period (T) in which a current flows from the anode (11) to the cathode and a non-current-flowing period (N) in which a current does not flow between the anode (11) and the cathode.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 28, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Yanagimoto, Motoki Hiraoka, Yuki Sato, Yoshitaka Shinmei
  • Patent number: 10153202
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10121757
    Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: November 6, 2018
    Assignee: Unimicron Technology Corp.
    Inventor: Cheng-Jui Chang
  • Patent number: 10103029
    Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 16, 2018
    Assignee: MacDermid Enthone Inc.
    Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Sean Xuan Lin, Theodore Antonellis
  • Patent number: 10074608
    Abstract: A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: September 11, 2018
    Assignees: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V., Technische Universität Berlin
    Inventors: Martin Wilke, Kai Zoschke, Markus Wöhrmann, Thomas Fritzsch, Hermann Oppermann, Oswin Ehrmann
  • Patent number: 10006144
    Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: June 26, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Huanfeng Zhu
  • Patent number: 9931820
    Abstract: This document discusses, among other things, a microelectronic system including a mold compound having a base layer and a surface layer on the base layer, and a seed layer deposited on the surface layer of the mold compound. The mold compound includes a monomer epoxy resin, a hardener, a filler material, and a polymer interphase material, wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the monomer epoxy resin and hardener alone.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli
  • Patent number: 9837356
    Abstract: Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 9520375
    Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi
  • Patent number: 9257401
    Abstract: A method of forming a semiconductor device includes forming an under-bump metallurgy (UBM) layer overlying a portion of a metal pad region within an opening of an encapsulating layer over a semiconductor substrate, and forming a bump layer overlying the UBM layer to fill the opening of the encapsulating layer. A removal process is initiated on an upper surface of the encapsulating layer and a coplanar top surface of the bump layer to remove the upper surface of the encapsulating layer until a top portion of the bump layer protrudes from the encapsulating layer.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: February 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Lei Hsu, Ming-Che Ho, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8883655
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignees: Intermoecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik
  • Patent number: 8877546
    Abstract: Methods and apparatus provide for a transistor, including: a semiconductor layer including molecules, protons, and/or ions, etc. diffused therein from a photoactive material; a channel disposed on or in the semiconductor layer; a source disposed on or in the semiconductor layer; a drain disposed on or in the semiconductor layer; and a gate electrically coupled to the semiconductor layer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 4, 2014
    Assignee: Corning Incorporated
    Inventors: Hon Hang Fong, Mingqian He
  • Patent number: 8697464
    Abstract: A method of manufacturing an optical semiconductor device includes: forming first and second optical semiconductor elements separated from each other by a separation groove on a semiconductor substrate; forming first and second electrodes containing Pt on top surfaces of the first and second optical semiconductor elements, respectively; forming a third electrode electrically connected to the first and second electrodes and preventing the third electrode from being formed in the separation groove; forming first and second Au plated layers on the first and second electrodes, respectively, by electrolytic plating, using the third electrode as a power supply layer; forming a resist covering the first and second Au plated layers by photolithography; and etching the third electrode, using the resist as a mask, to electrically separate the first electrode from the second electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Keisuke Matsumoto
  • Patent number: 8691597
    Abstract: An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Taku Kanaoka
  • Patent number: 8680682
    Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 8546275
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 1, 2013
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiang
  • Patent number: 8518826
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 27, 2013
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Fritz Redeker
  • Patent number: 8513750
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 8492216
    Abstract: The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: July 23, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8344513
    Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 8318534
    Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Alexander Gorer, Prashant Phatak, Tony Chiang, Igor Ivanov
  • Patent number: 8298936
    Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: October 30, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Bart van Schravendijk, Thomas Mountsier, Wen Wu
  • Patent number: 8288297
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 16, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiag
  • Patent number: 8247905
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
  • Patent number: 8129745
    Abstract: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external enviro
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: March 6, 2012
    Assignee: Nextron Corporation
    Inventors: Hak Beom Moon, Jin Hyung Cho, Suc Hyun Bang, Cheol Hwan Kim, Yoon Hyung Jang
  • Publication number: 20120018878
    Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, MIng-Che Ho, Chung-Shi Liu, Chien Ling Hwang, Cheng-Chung Lin, Hui-Jung Tsai, Zheng-Yi Lim
  • Patent number: 8076786
    Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 13, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Ying Hung, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong
  • Patent number: 8076241
    Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignees: Tokyo Electron Limited, Novellus Systems, Inc.
    Inventors: Frank M. Cerio, Jr., Shigeru Mizuno, Jonathan Reid, Thomas Ponnuswamy
  • Publication number: 20110256713
    Abstract: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and one or more polymerizable diluents, the diluents constituting at least 50% by weight of the composition.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert David Allen, Richard Anthony DiPietro, Geraud Jean-Michel Dubois, Mark Whitney Hart, Robert Dennis Miller, Ratnam Sooriyakumaran
  • Patent number: 7977152
    Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: July 12, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Alexander Gorer, Prashant Phatak, Tony Chiang, Igor Ivanov
  • Patent number: 7968379
    Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: June 28, 2011
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
  • Patent number: 7815786
    Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 19, 2010
    Assignee: Enthone Inc.
    Inventors: Vincent Paneccasio, Jr., Xuan Lin, Paul Figura, Richard Hurtubise
  • Patent number: 7807572
    Abstract: A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: October 5, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Varughese Mathew, Eddie Acosta, Ritwik Chatterjee, Sam S. Garcia
  • Patent number: 7736928
    Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 15, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Sergey Lopatin, John O. Dukovic, David Eaglesham, Nicolay Y. Kovarsky, Robert Bachrach, John Busch, Charles Gay
  • Patent number: 7732926
    Abstract: A method of manufacturing a through electrode. While using at least a first conductive film for a gate electrode as a mask, an inner trench and a peripheral trench is formed. The Inner trench is provided for an inner through electrode having a columnar semiconductor. The peripheral trench is provided for a peripheral through electrode around an annular semiconductor surrounding the inner trench. The inner trench and the peripheral trench are filled with a through electrode insulation film and a through electrode conductive film, respectively, to form an inner through electrode and a peripheral through electrode.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: June 8, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 7718522
    Abstract: A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: May 18, 2010
    Assignee: UTAC Thai Limited
    Inventors: Chalermsak Sumithpibul, Somchai Nondhasitthichai, Apichart Phaowongsa
  • Patent number: 7682966
    Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: March 23, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Bart van Schravendijk, Tom Mountsier, Wen Wu
  • Patent number: 7642156
    Abstract: Embodiments relate to a three-dimensional flash memory cell and method of forming the same that may be improve the uniformity of flash memory cell by removing a width difference of a polysilicon pattern when forming a floating gate of flash memory device, to thereby improve the reliability of semiconductor device. The process may be simplified due to the self-alignment in the step of forming the polysilicon pattern, which may improve the yield.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seong-Gyun Kim
  • Patent number: 7638431
    Abstract: A metal is deposited onto a surface electrochemically using a deposition solution including a metal salt. In making a composite nanostructure, the solution further includes an enhancer that promotes electrochemical deposition of the metal on the nanostructure. In a method of forming catalyzing nanoparticles, the metal preferentially deposits on a selected location of a surface that is exposed through a mask layer instead of on unexposed surfaces. A composite nanostructure apparatus includes an array of nanowires and the metal deposited on at least some nanowire surfaces. Some of the nanowires are heterogeneous, branched and include different adjacent axial segments with controlled axial lengths. In some deposition solutions, the enhancer one or both of controls oxide formation on the surface and causes metal nanocrystal formation. The deposition solution further includes a solvent that carries the metal salt and the enhancer.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 29, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Amir A. Yasseri, Theodore I. Kamins, Shashank Sharma
  • Patent number: 7633161
    Abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: December 15, 2009
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sung Ho Jang
  • Patent number: 7625815
    Abstract: An improved semiconductor device interconnect structure comprising a dielectric layer recessed with respect to the conductive interconnect features. This structure and method reduces embedded metallic residues from CMP scratches and metal cap applications and provides improved mechanical integrity at the capping layer/liner/dielectric interface.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 1, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 7608538
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
  • Patent number: 7595268
    Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwon Whan Han
  • Patent number: RE41538
    Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: August 17, 2010
    Inventor: James A. Cunningham