Abstract: Disclosed is a substrate treating apparatus. The substrate treating apparatus includes an imaging unit that photographs loci of the one or more discharge liquids discharged from the plurality of nozzles, and an inspection unit that calculates impact points of the one or more discharge liquids discharged from the plurality of nozzles and determines whether the impact points of the one or more discharge liquids discharged from the plurality of nozzles are normal. The inspection unit includes an image synthesizing unit that synthesizes a plurality of images captured by the imaging unit, a pre-processing unit that pre-processes image data generated through the image synthesizing unit, and a calculation unit that calculates whether the impact points of the one or more discharge liquids discharged from the plurality of nozzles are normal by comparing the image data pre-processed by the pre-processing unit.

Abstract: An electroplating apparatus includes: an electroplating bath including an anode region, in which an anode electrode is arranged, a cathode region and a membrane; a head unit including a contact ring holding a wafer and configured so that a first cathode potential is applied to the contact ring during an electroplating process; a reverse potential electrode arranged adjacent to the membrane and configured so that a second cathode potential is applied to the reverse potential electrode during the electroplating process, and a reverse cathode potential is applied to the reverse potential electrode during a rinsing process; and a power supply unit configured to apply the first cathode potential and the second cathode potential during the electroplating process, and further configured to apply the reverse cathode potential and a reverse anode potential to the anode electrode during the rinsing process.

Abstract: It is determined whether an imaginary component at a predetermined frequency of an alternating current impedance is equal to or more than a preliminarily set film-formable value or not. The metallic coating is formed in a state where the substrate is pressed by the solid electrolyte membrane when the imaginary component is equal to or more than the film-formable value in the determining. The metallic coating is formed in a state where the pressing of the substrate by the solid electrolyte membrane is released to separate the solid electrolyte membrane from the substrate, the solid electrolyte membrane is re-tensioned with a constant tensile force, and subsequently, the substrate is pressed by the re-tensioned solid electrolyte membrane when the imaginary component is smaller than the film-formable value in the determining.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: Process recipe data associated a process to be performed for a substrate at a process chamber is provided as input to a trained machine learning model. A set of process recipe settings for the process that minimizes scratching on one or more surfaces of the substrate is determined based on one or more outputs of the machine learning model. The process is performed for the substrate at the process chamber in accordance with the determined set of process recipe settings.

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: An electroplating copper layer includes bamboo-like copper crystal particles having a highly preferred orientation. The bamboo-like copper crystal particles have a long axis direction and a short axis direction, and the bamboo-like copper crystal particles have a length of 20 nm to 5 ?m in the long axis direction and a length of 20 nm to 2 ?m in the short axis direction. The bamboo-like copper crystal particles have a uniform particle size, and the electroplating copper layer has a major diffraction peak at a 2? angle of about 44°.

Abstract: The present disclosure provides an electroplating method, comprising providing an electroplating solution, wherein the electroplating solution includes an effective microorganisms aqueous solution and metal chloride; disposing a workpiece, wherein at least a part of the workpiece is in contact with the electroplating solution; and performing an electroplating process to electroplate metal of the metal chloride onto the workpiece.

Abstract: The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block.

Abstract: An electrochemical plating apparatus for depositing a conductive material on a wafer includes a cell chamber. The plating solution is provided from a bottom of the cell chamber into the cell chamber. A plurality of openings passes through a sidewall of the cell chamber. A flow regulator is arranged with each of the plurality of openings configured to regulate an overflow amount of the plating solution flowing out through the each of the plurality of openings. The electrochemical plating apparatus further comprises a controller to control the flow regulator such that overflow amounts of the plating solution flowing out through the plurality of openings are substantially equal to each other.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Abstract: A process for assembling microelectronic or semiconductor chips, comprising: providing a semiconductor chip having an active face with a connection pad; coating the active face of the semiconductor chip with a conformal dielectric material layer, such that the connection pad is completely coated by the conformal dielectric material layer; temporarily adhering the active face of the semiconductor chip to a carrier wafer; temporarily adhering the carrier wafer to a wafer-with-a-through-cavity such that the semiconductor chip extends into the through-cavity; assembling the semiconductor chip to the wafer-with-the-through-cavity by filling the through-cavity with a heat spreader material; releasing the assembled semiconductor chip and wafer-with-the-through-cavity from the carrier wafer; removing the conformal dielectric material layer from at least a portion of the connection pad; and forming an electrical connection to said at least a portion of the connection pad.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.

Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

Abstract: Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

Abstract: A method of forming a metal coating includes: disposing a solid electrolyte membrane (13) between an anode (11) and a substrate (B) which forms a cathode; bringing a solution (L) containing metal ions into contact with an anode-side portion of the solid electrolyte membrane (13); and causing, in a state where the solid electrolyte membrane (13) is in contact with the substrate (B), a current to flow from the anode (11) to the cathode so as to form a metal coating formed of the metal on the surface of the substrate (B). The metal coating is formed by repeating a current-flowing period (T) in which a current flows from the anode (11) to the cathode and a non-current-flowing period (N) in which a current does not flow between the anode (11) and the cathode.

Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.

Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.

Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

Abstract: A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.

Abstract: Methods, apparatus, and systems for depositing copper and other metals are provided. In some implementations, a wafer substrate is provided to an apparatus. The wafer substrate has a surface with field regions and a feature. A copper layer is plated onto the surface of the wafer substrate. The copper layer is annealed to redistribute copper from regions of the wafer substrate to the feature. Implementations of the disclosed methods, apparatus, and systems allow for void-free bottom-up fill of features in a wafer substrate.

Abstract: This document discusses, among other things, a microelectronic system including a mold compound having a base layer and a surface layer on the base layer, and a seed layer deposited on the surface layer of the mold compound. The mold compound includes a monomer epoxy resin, a hardener, a filler material, and a polymer interphase material, wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the monomer epoxy resin and hardener alone.

Abstract: Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.

Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.

Abstract: A method of forming a semiconductor device includes forming an under-bump metallurgy (UBM) layer overlying a portion of a metal pad region within an opening of an encapsulating layer over a semiconductor substrate, and forming a bump layer overlying the UBM layer to fill the opening of the encapsulating layer. A removal process is initiated on an upper surface of the encapsulating layer and a coplanar top surface of the bump layer to remove the upper surface of the encapsulating layer until a top portion of the bump layer protrudes from the encapsulating layer.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: Methods and apparatus provide for a transistor, including: a semiconductor layer including molecules, protons, and/or ions, etc. diffused therein from a photoactive material; a channel disposed on or in the semiconductor layer; a source disposed on or in the semiconductor layer; a drain disposed on or in the semiconductor layer; and a gate electrically coupled to the semiconductor layer.

Abstract: A method of manufacturing an optical semiconductor device includes: forming first and second optical semiconductor elements separated from each other by a separation groove on a semiconductor substrate; forming first and second electrodes containing Pt on top surfaces of the first and second optical semiconductor elements, respectively; forming a third electrode electrically connected to the first and second electrodes and preventing the third electrode from being formed in the separation groove; forming first and second Au plated layers on the first and second electrodes, respectively, by electrolytic plating, using the third electrode as a power supply layer; forming a resist covering the first and second Au plated layers by photolithography; and etching the third electrode, using the resist as a mask, to electrically separate the first electrode from the second electrode.

Abstract: An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount.

Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.

Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external enviro

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.