Conductor Layer Next To Insulator Is Metallic Silicide (me Si) (epo) Patents (Class 257/E21.203)
  • Patent number: 9882023
    Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyun-Ming Lin, Hua Feng Chen, Kuo-Hua Pan, Min-Yann Hsieh, C. H. Wu
  • Patent number: 9773706
    Abstract: A semiconductor device includes a semiconductor substrate, at least a first field-effect structure integrated in the semiconductor substrate and at least a second field-effect structure integrated in the semiconductor substrate. The first field-effect structure includes a first gate electrode comprised of a polycrystalline semiconductor material. The second field-effect structure includes a second gate electrode comprised of one of a metal, a metal alloy, a metal layer stack, a metal alloy layer stack and any combination thereof.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Walter Rieger
  • Patent number: 8778795
    Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ronny Pfuetzner, Jens Heinrich
  • Patent number: 8659066
    Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8652898
    Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8569170
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Patent number: 8513765
    Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8334574
    Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Keun Park
  • Patent number: 8330234
    Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 11, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Hase
  • Patent number: 8304841
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeff J. Xu, Cheng-Tung Lin, Hsiang-Yi Wang, Wen-Chin Lee, Betty Hsieh
  • Patent number: 8299542
    Abstract: A field-effect transistor is provided. The field-effect transistor includes a gate structure including a fully silicided gate material overlying a gate dielectric disposed on a substrate, the fully silicided gate material having an upper region and a lower region, wherein the lower region has a first lateral dimension in accordance with a lateral dimension of the gate dielectric, and the upper region has a second lateral dimension different from the first lateral dimension.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Zhijiong Luo, Huilong Zhu
  • Patent number: 8084142
    Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu, H. Montgomery Manning
  • Patent number: 7964907
    Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sam-jong Choi, Yong-kwon Kim, Kyoo-chul Cho, Kyung-soo Kim, Jae-ryong Jung, Tae-soo Kang, Sang-Sig Kim
  • Patent number: 7892961
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Cheng-Tung Lin, Liang-Gi Yao
  • Patent number: 7858524
    Abstract: A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama
  • Patent number: 7812415
    Abstract: A semiconductor device including a gate insulating layer formed over a semiconductor substrate; a gate insulating layer pattern formed over an exposed uppermost surface of the semiconductor substrate along the same horizontal plane as the gate insulating layer; an isolation insulating layer formed over the gate insulating layer; a plurality of first gate conductive patterns formed over the gate insulating layer and the gate insulating layer pattern; a source/drain conductor formed over an exposed uppermost surface of the semiconductor substrate; a second gate conductive pattern formed over one of the plurality of the first gate conductive patterns that is provided over the gate insulating layer pattern; a plurality of salicide layers formed over the second gate conductive pattern, the source/drain conductor, and at least one of the plurality of first gate conductive patterns that are provided over the gate insulating layer; and a pair of spacers formed over the gate insulating layer pattern and on sidewalls o
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: October 12, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong-Ho Park
  • Publication number: 20100248463
    Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Inventors: Tobias Letz, Frank Feustel, Kai Frohberg
  • Patent number: 7754593
    Abstract: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping the second gate electrode covered; etching an upper part of the first gate electrode by using the mask material as a mask; removing the mask material; depositing a metal film on the first gate electrode and the second gate electrode; and siliciding the whole of the first gate electrode and an upper part of the second gate electrode.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohiro Saito
  • Patent number: 7700438
    Abstract: Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chun-Li Liu, Tushar P. Merchant, Marius K. Orlowski, Matthew W. Stoker
  • Patent number: 7611943
    Abstract: A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor (124) into the barrier material (118). An integrated circuit has a gate dielectric (116), a doped metallic barrier material (118, 126N and/or 126P) on the gate dielectric (116), and metal silicide (180) on the metallic barrier material (118). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Kaiping Liu
  • Publication number: 20090239344
    Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 24, 2009
    Inventors: Yong Kuk Jeong, Bong-Seok Suh, Dong-Hee Yu, Oh-Jung Kwon, Seong-Dong Kim, O Sung Kwon
  • Publication number: 20090159992
    Abstract: A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favoured for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).
    Type: Application
    Filed: June 13, 2006
    Publication date: June 25, 2009
    Applicant: NXP B.V.
    Inventor: Bartlomiej J. Pawlak
  • Publication number: 20090090986
    Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.
    Type: Application
    Filed: December 15, 2008
    Publication date: April 9, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Haining Yang
  • Publication number: 20090081869
    Abstract: A process for producing a silicon compound can minimize the number of steps and can form a desired compound in a low-temperature environment. The process comprises: allowing a radical of a halogen gas to act on a member 11 to be etched, which is disposed within a chamber 1 and is formed of a material containing an element capable of forming a compound with Si, while keeping the member 11 at a relatively high temperature, to form a gas of a precursor 24, which is a compound of the material and the halogen; holding a substrate 3 accommodated within the chamber 1 at a relatively low temperature, with the Si interface of the substrate 3 being exposed, to adsorb the precursor 24 onto the Si interface of the substrate 3; and then allowing the radical of the halogen gas to act on the precursor 24 adsorbed onto the Si interface to reduce the precursor 24, thereby producing a compound of the material and Si.
    Type: Application
    Filed: May 17, 2006
    Publication date: March 26, 2009
    Inventors: Yoshiyuki Ooba, Hitoshi Sakamoto
  • Publication number: 20090020829
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 22, 2009
    Inventors: Aditi CHANDRA, Arvind KAMATH, James Montague CLEEVES, Joerg ROCKENBERGER, Mao Takashima, Erik SCHER
  • Publication number: 20080293226
    Abstract: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film; forming a mask material so as to expose an upper surface of the first gate electrode while keeping the second gate electrode covered; etching an upper part of the first gate electrode by using the mask material as a mask; removing the mask material; depositing a metal film on the first gate electrode and the second gate electrode; and siliciding the whole of the first gate electrode and an upper part of the second gate electrode.
    Type: Application
    Filed: August 3, 2007
    Publication date: November 27, 2008
    Inventor: Tomohiro Saito
  • Patent number: 7436075
    Abstract: The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and emits an ion beam 4 which is larger in width than a substrate 6, to the substrate 6. The substrate driving mechanism 30 reciprocally drives the substrate 6 in the vacuum chamber 10. The center axes 14a of the rotation shafts 14 are located in a place separated from the ion source 2 toward the substrate, and substantially parallel to the surface of the substrate. The arms 12 are disposed inside the vacuum chamber 10, and support the ion source 2 through the rotation shafts 14. The motor is disposed outside the vacuum chamber 10, and reciprocally rotates the rotation shaft 14.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 14, 2008
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventor: Yasunori Ando
  • Patent number: 7429526
    Abstract: A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: September 30, 2008
    Assignee: Xilinx, Inc.
    Inventors: Deepak Kumar Nayak, Yuhao Luo
  • Publication number: 20080227279
    Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps
    Type: Application
    Filed: March 14, 2008
    Publication date: September 18, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takashi HASE
  • Patent number: 7399670
    Abstract: A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Taek-Soo Jeon, Yu-Gyun Shin, Sang-Bom Kang, Hong-Bae Park, Hag-Ju Cho, Hye-Lan Lee, Beom-Jun Jin, Seong-Geon Park
  • Patent number: 7358181
    Abstract: A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts selectively on the first reaction products, whereby the structuring takes place in a vertical direction.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: April 15, 2008
    Assignee: Atmel Germany GmbH
    Inventor: Christoph Bromberger
  • Patent number: 7341933
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: March 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Haowen Bu, Jiong-Ping Lu, Lindsey Hall
  • Patent number: 7271455
    Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan, Vamsi Paruchuri, Ghavam G. Shahidi, Michelle L. Steen, Clement H. Wann
  • Patent number: 7256125
    Abstract: For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 ??cm.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 14, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kentaro Yamada, Masato Takahashi, Tatsuyuki Konagaya, Takeshi Katoh, Masaki Sakashita, Koichiro Takei, Yasuhiro Obara, Yoshio Fukayama
  • Patent number: 7256123
    Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: August 14, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7235472
    Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 26, 2007
    Assignee: Infineon Technologies AG
    Inventors: Veit Klee, Sun-Oo Kim
  • Patent number: 7220662
    Abstract: Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 22, 2007
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Sunfei Fang, Zhijiong Luo
  • Patent number: 7208409
    Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Duofeng Yue, Xiaozhan Liu, Donald S. Miles, Lance S. Robertson
  • Patent number: 7183187
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310).
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: February 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Gregory Shinn, Ping Jiang
  • Patent number: 6794713
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima