Insulator Formed On Silicon Semiconductor Body (epo) Patents (Class 257/E21.191)

  • Patent number: 11245019
    Abstract: A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: February 8, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Woo-Song Ahn, Sang-Don Yi, Yongchul Oh
  • Patent number: 10643841
    Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon (a-Si) film that involves pretreating the surface of the substrate to modify the underlying hydroxy-terminated silicon (Si—OH) or hydrogen-terminated silicon (Si—H) surface to oxynitride-terminated silicon (Si—ON) or nitride-terminated silicon (Si—N) and enhance the subsequent a-Si deposition are provided. First, a substrate having features formed in a first surface of the substrate is provided. The surface of the substrate is then pretreated to enhance the surface of the substrate for the flowable deposition of amorphous silicon that follows. A flowable deposition process is then performed to deposit a flowable silicon layer over the surface of the substrate. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition process to realize seam-free gapfilling between features with high quality amorphous silicon film.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 5, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Shishi Jiang, Abhijit Basu Mallick
  • Patent number: 10483102
    Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon (a-Si) film that involves pretreating the surface of the substrate to modify the underlying hydroxy-terminated silicon (Si—OH) or hydrogen-terminated silicon (Si—H) surface to oxynitride-terminated silicon (Si—ON) or nitride-terminated silicon (Si—N) and enhance the subsequent a-Si deposition are provided. First, a substrate having features formed in a first surface of the substrate is provided. The surface of the substrate is then pretreated to enhance the surface of the substrate for the flowable deposition of amorphous silicon that follows. A flowable deposition process is then performed to deposit a flowable silicon layer over the surface of the substrate. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition process to realize seam-free gapfilling between features with high quality amorphous silicon film.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Shishi Jiang, Abhijit Basu Mallick
  • Patent number: 10079314
    Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 18, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Charel Levy, Frederick B. Jenne, Krishnaswamy Ramkumar
  • Patent number: 9847222
    Abstract: Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Patrick Reilly, Harald te Nijenhuis, Nerissa Draeger, Bart J. van Schravendijk, Nicholas Muga Ndiege
  • Patent number: 9530856
    Abstract: A novel semiconductor device with a transistor using an oxide semiconductor film, in which a conductive film including Cu is used as a wiring or the like, is provided. The semiconductor device includes a first insulating film, an oxide semiconductor over the first insulating film, a gate electrode overlapping the oxide semiconductor with a gate insulating film positioned therebetween, a second insulating film in contact with a side surface of the gate electrode, and a third insulating film in contact with a top surface of the gate electrode. The gate electrode includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, Ti, Zr, Mg, Ca, or a mixture of two or more of these elements).
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidekazu Miyairi
  • Publication number: 20140120708
    Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Min Dai, Xiang Hu, Jinping Liu, Yanxiang Liu, Xiaodong Yang
  • Publication number: 20140106554
    Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
  • Publication number: 20130140634
    Abstract: A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Christopher D'Emic, Young-Hee Kim, Dae-gyu Park, Jeng-Bang Yau
  • Patent number: 8450218
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Brent Gilgen
  • Publication number: 20130062736
    Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: JEFFREY E. BRIGHTON, JEFFREY A. WEST, RAJESH TIWARI
  • Patent number: 8367559
    Abstract: Characteristics of a low-k insulating film grown on a substrate is modulated in the thickness-wise direction, by varying the ratio of high-frequency input and low-frequency input used for inducing plasma in the course of forming the film, to thereby improve the adhesion strength while keeping the dielectric constant at a low level, wherein the high-frequency input and the low-frequency input for inducing plasma are applied from a single electrode, while elevating the level of low-frequency input at least either at the start of formation or at the end of formation of the insulating film, as compared with the input level in residual time zone.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Yoshihiro Hayashi
  • Publication number: 20120299089
    Abstract: It is disclosed a semiconductor device and a method for manufacturing the same. One method comprises providing a semiconductor layer that is formed on an insulating layer; forming a mask pattern on the semiconductor layer, which exposes a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer of a predetermined thickness, thereby forming a groove; forming a gate stack in the mask pattern and the groove; removing the mask pattern to expose a portion of sidewalls of the gate stack. The method not only meets the requirement for a precise thickness of the SOI, but also increases the thickness of the source/drain regions as compared to a device having a uniform SOI thickness at the gate stack, thereby facilitating a reduction of the parasitic resistance of the source/drain regions.
    Type: Application
    Filed: August 9, 2011
    Publication date: November 29, 2012
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Publication number: 20120238086
    Abstract: When forming sophisticated high-k metal gate electrode structures, for instance on the basis of a replacement gate approach, superior interface characteristics may be obtained on the basis of using a thermally grown base material, wherein the electrically effective thickness may be reduced on the basis of a low temperature anneal process. Consequently, the superior interface characteristics of a thermally grown base material may be provided without requiring high temperature anneal processes, as are typically applied in conventional strategies using a very thin oxide layer formed on the basis of a wet oxidation chemistry.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Klaus Hempel, Robert Binder, Joachim Metzger
  • Patent number: 8268712
    Abstract: A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the work function metal layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 18, 2012
    Assignee: United Microelectronics Corporation
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Publication number: 20120220092
    Abstract: Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 30, 2012
    Applicant: VISHAY-SILICONIX
    Inventors: Madhur Bobde, Qufei Chen, Misbah Ul Azam, Kyle Terrill, Yang Gao, Sharon Shi
  • Publication number: 20120217578
    Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
    Type: Application
    Filed: May 8, 2012
    Publication date: August 30, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Soon Lim, Meng-Hsuan Chan, Kuang-Yuan Hsu
  • Publication number: 20120098052
    Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 26, 2012
    Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
  • Patent number: 8114739
    Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8105956
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Brent Gilgen
  • Publication number: 20110254898
    Abstract: A liquid discharge head includes an electric contact electrically connected with a liquid discharge device; a first semiconductor substrate having an energy generation element for generating energy to discharge a liquid, and a driver unit including a first transistor and configured to drive the energy generation element; and a second semiconductor substrate having a receiving unit configured to possess a second transistor and receive a signal serially transmitted via the electric contact, and an expansion unit configured to possess a third transistor and parallel-convert the signal received in the receiving unit to generate a signal to control the driver unit, wherein a gate oxide film in the first transistor is thicker than a gate oxide film in the second transistor and a gate oxide film in the third transistor.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 20, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Chiaki Muraoka, Yukuo Yamaguchi
  • Patent number: 8021990
    Abstract: A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Luigi Colombo, Mark R Visokay, Rajesh Khamankar, Douglas E Mercer
  • Publication number: 20110212579
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Application
    Filed: May 4, 2011
    Publication date: September 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Patent number: 7884032
    Abstract: A system, method and apparatus is capable of producing layers of various materials stacked on one another on a substrate without exposing the substrate to the pressure and contaminants of ambient air until the stack is complete. In one aspect, the stack of layers can include both an insulative layer of one or more insulative films, and a conductive metal layer of one or more conductive metal layer films. In another aspect, a bias signal of positive and negative voltage pulses may be applied to a target of a deposition chamber to facilitate deposition of the target material in a suitable fashion. In yet another aspect, one or more of the deposition chambers may have associated therewith a pump which combines a turbomolecular pump and a cryogenic pump to generate an ultra high vacuum in that chamber. Other features are described and claimed.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: February 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Mengqi Ye, Peijun Ding, Hougong Wang, Zhendong Liu
  • Patent number: 7872312
    Abstract: A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate insulating film includes a first high dielectric constant insulating film with a first nitrogen concentration and the second gate insulating film includes a second high dielectric constant insulating film with a second nitrogen concentration higher than the first nitrogen concentration.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Hisashi Ogawa
  • Patent number: 7825040
    Abstract: A method of filling a recess with an insulation film includes: introducing an alkoxysilane or aminosilane precursor containing neither a Si—C bond nor a C—C bond into a reaction chamber where a substrate having an irregular surface including a recess is placed; and depositing a flowable Si-containing insulation film on the irregular surface of the substrate to fill the recess therewith by plasma reaction at ?50° C. to 100° C.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 2, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Hisashi Tazawa, Jeongseok Ha, Shintaro Ueda
  • Publication number: 20100203714
    Abstract: It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure where a drain, a gate and a source are arranged in a vertical direction with respect to a substrate, and the gate is formed to surround a pillar-shaped semiconductor layer.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 12, 2010
    Inventors: Fujio Masuoka, Shintaro Arai
  • Patent number: 7727911
    Abstract: In formation of a gate insulating film made of a high dielectric constant metal silicate, atomic layer deposition (ALD) is performed by setting exposure time to a precursor containing a metal or the like to saturation time of a deposition rate by a surface adsorption reaction and by setting exposure time to an oxidizing agent to time required for a composition of a metal oxide film to reach 97% or more of a stoichiometric value.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Kenji Yoneda, Kazuhiko Yamamoto
  • Patent number: 7682852
    Abstract: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light emission face of the light emission structure; removing the light shield film corresponding to an area of the light emission face of the light emission structure including and above the first clad layer; and removing the protection layer.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Led Co., Ltd.
    Inventors: Han-youl Ryu, Kyoung-ho Ha, Youn-joon Sung
  • Patent number: 7556970
    Abstract: A damaged layer repairing method repairs a damaged layer formed in a surface of a SiOCH film having a low dielectric constant film, containing silicon, carbon, oxygen and hydrogen and formed on a substrate through the elimination of carbon atoms by the decarbonizing effect of plasmas used in an etching process and an ashing process. CH3 radicals are produced through the thermal decomposition of C8H18O2 gas represented by a structural formula: (CH3)3COOH(CH3)3. CH3 radicals are brought into contact with the damaged layer in the SiOCH film and are made to bond to the damaged layer to repair the damaged layer.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: July 7, 2009
    Assignees: Tokyo Electron Limited, National University Corporation, Nagoya University
    Inventors: Masaru Hori, Kazuhiro Kubota
  • Patent number: 7538001
    Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
  • Publication number: 20090101965
    Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 23, 2009
    Applicant: Nanosys, Inc.
    Inventors: Jian Chen, Rahul Sharangpani
  • Patent number: 7514376
    Abstract: A method for manufacturing a semiconductor device is disclosed which enables to suppress decrease in the mobility in a channel region by suppressing piercing of boron through a gate insulation film which boron is ion-implanted into a gate electrode. The method for manufacturing a semiconductor device includes: a step for forming a gate insulating layer on an active region of a semiconductor substrate; a step for introducing nitrogen through the front surface of the gate insulating layer using active nitrogen; and a step for conducting an annealing treatment in an NO gas atmosphere so that the nitrogen concentration distribution in the nitrogen-introduced gate insulating layer is high on the front surface side and low on the side of the interface with the semiconductor substrate.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Mitsuaki Hori
  • Publication number: 20090029528
    Abstract: The present invention generally provides apparatus and method for forming a clean and damage free surface on a semiconductor substrate. One embodiment of the present invention provides a system that contains a cleaning chamber that is adapted to expose a surface of substrate to a plasma cleaning process prior to forming an epitaxial layer thereon. In one embodiment, a method is employed to reduce the contamination of a substrate processed in the cleaning chamber by depositing a gettering material on the inner surfaces of the cleaning chamber prior to performing a cleaning process on a substrate. In one embodiment, oxidation and etching steps are repeatedly performed on a substrate in the cleaning chamber to expose or create a clean surface on a substrate that can then have an epitaxial placed thereon. In one embodiment, a low energy plasma is used during the cleaning step.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 29, 2009
    Inventors: Errol Antonio C. SANCHEZ, Johanes SWENBERG, David K. CARLSON, Roisin L. DOHERTY
  • Patent number: 7476600
    Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: January 13, 2009
    Assignee: Translucent, Inc.
    Inventor: Petar B. Atanackovic
  • Patent number: 7476627
    Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 13, 2009
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
  • Patent number: 7446055
    Abstract: This invention relates to an improvement in a deposition process for producing low dielectric films having a dielectric constant of 3, preferably <2.7 and lower. The process comprises the steps: (a) forming a liquid precursor solution comprised of an organosilicon source containing both Si—O and Si—C bonds and solvent; (b) generating a liquid mist of said liquid precursor solution, said mist existing as precursor solution droplets having a number average droplet diameter size of less than 0.5 ?m; (c) preferably electrically charging the liquid mist of said liquid precursor solution droplets; (d) depositing liquid mist of said liquid precursor solution droplets onto a substrate; and, (e) converting the thus deposited liquid mist of said liquid precursor solution droplets to a solid, low dielectric film.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 4, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Scott Jeffrey Weigel, Jean Louise Vincent, Sarah Kathryn Coulter, James Edward MacDougall
  • Patent number: 7410910
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. The lanthanum aluminum oxynitride film may be formed by atomic layer deposition.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7323729
    Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: January 29, 2008
    Assignee: Promos Technologies Inc.
    Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao
  • Publication number: 20070141765
    Abstract: In an array substrate and an LCD apparatus having the same, the array substrate includes a signal line, a first insulating layer formed on the signal line, and a pixel electrode formed on the first insulating layer and overlapped with the signal line. The pixel electrode is electrically connected with the signal line so as to discharge a signal through the signal line. A second insulating layer is disposed between the pixel electrode and the first insulating layer, and includes an opening formed in an overlapped area of the pixel electrode and the signal line so as to partially expose the first insulating layer. Thus, the LCD apparatus may have an enhanced display quality.
    Type: Application
    Filed: February 16, 2007
    Publication date: June 21, 2007
    Inventors: Yong-Ho Yang, Joo-Sun Yoon, Kyo-Seop Choo, Jin-Suk Park
  • Patent number: 7160786
    Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: January 9, 2007
    Assignee: Kawaski Microelectronics, Inc.
    Inventor: Yoshitaka Kimura