Lithography, Isolation, Or Planarization-related Aspects Of Making Conductor-insulator-semiconductor Structure, E.g., Sub-lithography Lengths; To Solve Problems Arising At Crossing With Side Of Device Isolation (epo) Patents (Class 257/E21.206)
  • Patent number: 10971372
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Subhadeep Kal, Nihar Mohanty, Angelique D. Raley, Aelan Mosden, Scott W. Lefevre
  • Patent number: 10971595
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for fabricating the MOSFET are disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 6, 2021
    Assignee: Nexchip Seminconductor Corporation
    Inventor: Geeng-Chuan Chern
  • Patent number: 10884306
    Abstract: The present disclosure provides a method for manufacturing an array substrate and a display device. The method for manufacturing the array substrate includes providing a substrate; disposing a metal layer material on the substrate; disposing thermal reactive photoresist material on the metal layer material; obtaining a thermal reactive photoresist layer using a mask process and a thermal reaction process; and obtaining a metal layer by an etching process.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 5, 2021
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chung-Kuang Chien
  • Patent number: 10804364
    Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vibhor Jain, Qizhi Liu, John J. Pekarik
  • Patent number: 10692887
    Abstract: In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10672893
    Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hung Lin, Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 10658478
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Patent number: 10497575
    Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 3, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Jeffrey Shearer
  • Patent number: 10483073
    Abstract: The present disclosure relates to methods of fabricating electronic devices or components thereof. The electronic devices can be vacuum electronic devices. The methods can include disposing a first material on or in a substrate. The methods can further include removing a portion of the first material to form one or more structure protruding from the substrate. The methods can further include disposing a second material onto the one or more structure of the first material, and then removing a portion of the second material to form one or more sidewall structures. A second portion of the one or more structures of the first material can also be removed to form a fabricated structure including the substrate and one or more sidewall structures protruding therefrom.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 19, 2019
    Assignee: Elwha LLC
    Inventors: Andrew T. Koch, Andrew R. Lingley, Max N. Mankin, Tony S. Pan
  • Patent number: 10361280
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10204960
    Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Chia, Chun-Hao Chou, Kai-Chun Hsu, Kuo-Cheng Lee, Shyh-Fann Ting
  • Patent number: 10166914
    Abstract: A display article includes a film formed from a stretchable plastic and including a first plurality of micro-light emitting diodes and a second plurality of micro-light emitting diodes disposed adjacent to the first plurality and embedded in the plastic. The article includes a substrate having a first portion and a second portion, and a tear seam disposed between the first and second portions. The film is attached to the substrate such that the tear seam is located between the first and second pluralities. A component includes the display article and an airbag disposed adjacent the substrate and configured for transitioning between a stowed position in which the airbag does not extend through the substrate, and a deployed position in which the airbag extends through the substrate and the film. The first and second portions are separated at the tear seam when the airbag is disposed in the deployed position.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 1, 2019
    Assignee: GM Global Technology Operations LLC
    Inventors: Robert C. Jablonski, Jason E. Diehl, Thomas A. Seder, James A. Carpenter
  • Patent number: 10026621
    Abstract: Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber. The methods may include forming an inert plasma within the processing region of the processing chamber. Effluents of the inert plasma may be utilized to modify the oxidized silicon nitride. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified oxidized silicon nitride from the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 17, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jungmin Ko, Tom Choi, Nitin Ingle, Kwang-Soo Kim, Theodore Wou
  • Patent number: 9926187
    Abstract: Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: March 27, 2018
    Assignee: NXP USA, Inc.
    Inventors: Chad S Dawson, Dubravka Bilic, Lianjun Liu, Andrew C McNeil
  • Patent number: 9892917
    Abstract: Methods and apparatus for depositing nanolaminate films are provided. In various embodiments, the nanolaminate film may be deposited over a core layer, which may be patterned. The nanolaminate film may act as a spacer while performing a double or quadruple patterning process. The nanolaminate film may include at least two different types of film. In some cases, the two different types of film have different compositions. In some cases, the two different types of film may be deposited under different deposition conditions, and may or may not have the same composition. After the nanolaminate film is deposited, the substrate may be etched to expose the core layer. Some portions of the nanolaminate film (e.g., portions that form on sidewalls of features patterned in the core layer) may remain after etching, and may serve as a mask during later processing steps in a double or quadruple patterning process.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 13, 2018
    Assignee: Lam Research Corporation
    Inventors: Shankar Swaminathan, Frank L. Pasquale, Adrien LaVoie
  • Patent number: 9853109
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Patent number: 9799686
    Abstract: MMIC circuits with thin film transistors are provided without the need of grinding and etching of the substrate after the fabrication of active and passive components. Furthermore, technology for active devices based on non-toxic compound semiconductors is provided. The success in the MMIC methods and structures without substrate grinding/etching and the use of semiconductors without toxic elements for active components will reduce manufacturing time, decrease economic cost and environmental burden. MMIC structures are provided where the requirements for die or chip attachment, alignment and wire bonding are eliminated completely or minimized. This will increase the reproducibility and reduce the manufacturing time for the MMIC circuits and modules.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 24, 2017
    Inventors: Ishiang Shih, Cindy X. Qiu, Chunong Qiu, Yi-Chi Shih
  • Patent number: 9793208
    Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Haifeng Sheng, Juan Boon Tan, Wanbing Yi, Daxiang Wang, Soh Yun Siah
  • Patent number: 9735548
    Abstract: A semiconductor laser element includes a semiconductor structure having an optical cavity and a protective film. The semiconductor structure includes a pair of stepped parts at both ends of the semiconductor structure in a cavity width direction, and a first texture pattern extending in a cavity length direction on a bottom surface of each of the stepped parts. The first texture pattern includes recesses and/or protrusions along the cavity length direction. The protective film covers at least part of the first texture pattern to define a second texture pattern having upper surfaces and bottom surfaces. A length of the bottom surfaces of the second texture pattern is less than a height from the bottom surfaces to a surface of the semiconductor structure. A length of the upper surfaces of the second texture pattern is less than a height from the upper surfaces to the surface of the semiconductor structure.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 15, 2017
    Assignee: Nichia Corporation
    Inventors: Susumu Harada, Yasuhiro Kawata
  • Patent number: 9721887
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a trench in the dielectric layer, forming a first barrier layer in the trench. The first barrier layer has a first portion disposed along sidewalls of the trench and a second portion disposed over a bottom of the trench. The method also includes applying an anisotropic plasma treatment to convert the second portion of the first barrier layer into a second barrier layer, removing the second barrier layer while the first portion of the first barrier layer is disposed along sidewalls of the trench. The method also includes forming a conductive feature in the trench.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chao-Hsien Peng, Chih Wei Lu, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 9722044
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Toshiaki Iwamatsu
  • Patent number: 9553425
    Abstract: A method of manufacturing a plurality of semiconductor laser elements having; preparing the semiconductor wafer; forming grooves that extend along second lines on a first main surface side of the semiconductor wafer, and forming a first texture pattern along second lines on a bottom surface of the grooves, the second lines being parallel to a cavity length direction; forming a second texture pattern along the second lines by covering at least part of the first texture pattern with a protective film; and splitting the semiconductor wafer along first lines, the first lines being parallel to a cavity width direction, and splitting along the second lines using a second main surface, which is an opposite side of the first main surface, of the semiconductor wafer as an origin.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Susumu Harada, Yasuhiro Kawata
  • Patent number: 9478467
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 25, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Richard J. De Souza, Patrice M. Parris
  • Patent number: 9391286
    Abstract: An exemplary embodiment provides a stretchable display device which is stretched in at least one direction. The stretchable display device according to the exemplary embodiment includes a stretchable substrate, a display unit, a plurality of rigid lenses, and a transparent elastic part. The display unit is on the stretchable substrate, and includes a plurality of light sources and a plurality of stretchable electrodes. The rigid lenses are disposed to correspond to the plurality of light sources, respectively. The transparent elastic part encloses the plurality of rigid lenses on the display unit and is stretched along with the stretched substrate and when being stretched, forms lens surfaces corresponding to the plurality of rigid lenses, respectively.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Joong Kwon, Chi-O Cho, Sang-Il Park
  • Patent number: 9385214
    Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Young Liao, Yi-Jen Chen, Yung Jung Chang
  • Patent number: 9379214
    Abstract: A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: June 28, 2016
    Assignee: Semi Solutions LLC
    Inventors: Ashok K. Kapoor, Robert J. Strain
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8999862
    Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
  • Patent number: 8981441
    Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
  • Patent number: 8872241
    Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8841205
    Abstract: A manufacturing method for a semiconductor device, comprising: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first processing; obtaining a processed amount with respect to each of the plurality of wafers by second processing in a second processing apparatus after the first processing; deciding a second processing order, which is different from the first processing order, from the processed amount with respect to each of the plurality of wafers by the first processing and the processed amount with respect to each of the plurality of wafers by the second processing; and performing the second processing on the plurality of wafers in the second processing order in the second processing apparatus.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Kamimura, Takashi Shimizu, Kunihiro Miyazaki
  • Patent number: 8703575
    Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8680671
    Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: March 25, 2014
    Assignee: Spansion LLC
    Inventor: Tzu-Yen Hsieh
  • Patent number: 8598042
    Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lun Lu, Kuan-Wen Lin, Ching-Wei Shen, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 8574926
    Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
  • Patent number: 8501608
    Abstract: The present invention relates to a method for processing semiconductor devices with a fine structure, and more particularly, to a processing method suitable for miniaturizing semiconductor devices with a so-called high-k/metal gate structure. In an embodiment of the present invention, a deposited film, which includes an insulating film made of Hf or Zr and a material of Mg, Y or Al existing on, under or in the insulating film, is formed on a Si substrate and is removed by repeating a dry etching process and a wet etching process at least one time. The wet etching process is performed prior to the dry etching process.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 6, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tetsuo Ono, Tetsu Morooka
  • Patent number: 8450169
    Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Ramachandra Divakaruni, Siddarth A. Krishnan, Ravikumar Ramachandran
  • Patent number: 8394714
    Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Lexmark International, Inc.
    Inventor: Byron V. Bell
  • Patent number: 8324119
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
  • Publication number: 20120187563
    Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Hsueh HSIEH, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
  • Patent number: 8173548
    Abstract: A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng Hung, Yung-Sung Yen, Chun-Kuang Chen
  • Patent number: 8120139
    Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: February 21, 2012
    Assignee: International Rectifier Corporation
    Inventor: Paul Bridger
  • Patent number: 8114727
    Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Zhiqiang Wu, Xin Wang
  • Patent number: 8072023
    Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: December 6, 2011
    Assignee: Marvell International Ltd.
    Inventor: Chih-Hsin Wang
  • Patent number: 8043948
    Abstract: A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 25, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yuji Setta
  • Patent number: 7972875
    Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 5, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John Rogers, Ralph Nuzzo, Matthew Meitl, Etienne Menard, Alfred J. Baca, Michael Motala, Jong-Hyun Ahn, Sang-II Park, Chang-Jae Yu, Heung-Cho Ko, Mark Stoykovich, Jongseung Yoon
  • Patent number: 7968421
    Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: June 28, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Jung Shin
  • Patent number: 7910443
    Abstract: A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern over the resultant structure in the cell region, exposing the peripheral region, trimming the hard mask patterns in the peripheral region, removing the mask pattern, and etching the conductive material layer to form gate patterns using the hard mask patterns.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun-Seok Cho
  • Patent number: 7875987
    Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, Trevor Joseph Timpane
  • Patent number: 7855410
    Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon