Plasma Etching; Reactive-ion Etching (epo) Patents (Class 257/E21.218)
  • Patent number: 10892404
    Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel Charles Edelstein
  • Patent number: 10825682
    Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 3, 2020
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Vasile Paraschiv, Efrain Altamirano Sanchez, Zheng Tao
  • Patent number: 10699939
    Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate including device regions and isolation regions, adjacent with one another; providing discrete fins on the substrate, pitches between adjacent fins being substantially same; forming a protective layer on the sidewalls of the fins; removing a partial thickness of the fins in the isolation regions along with a partial thickness of the protective layer in the isolation regions by a first etching process; forming dummy fins by a second etching process to etch the remaining fins in the isolation regions using the remaining protective layers as a mask; removing the remaining protective layer after the second etching process; and forming isolation structures in the isolation regions on the substrate. The isolation structures have a top lower than the fins in the device regions and higher than the dummy fins in the isolation regions.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hua Yong Hu, Yi Shih Lin
  • Patent number: 10692880
    Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about ?100° C. to about 100° C.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 23, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhenjiang Cui, Hanshen Zhang, Anchuan Wang, Zhijun Chen, Nitin K. Ingle
  • Patent number: 10559859
    Abstract: According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier; and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Marko Lemke, Stefan Tegen
  • Patent number: 10541184
    Abstract: Embodiments may include a method of etching. The method may also include flowing a gas mixture through a plasma discharge to form plasma effluents. The method may further include flowing the plasma effluents through a plurality of apertures to a layer on a substrate. The layer may have a first thickness. In addition, the method may include etching the layer with the plasma effluents. The method may also include measuring the intensity of emission from a reaction of plasma effluents with the layer. The method may further include summing the intensity of the emission while the plasma effluents are being flowed to the layer to obtain an integrated intensity. The method may then include comparing the integrated intensity to a reference value corresponding to a target etch thickness. The method may include extinguishing the plasma discharge when the integrated intensity is equal to or greater than the reference value.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: January 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Soonwook Jung, Soonam Park, Dmitry Lubomirsky
  • Patent number: 10431625
    Abstract: An image sensor may include: a trench formed in a substrate; an impurity region formed in the substrate to be in contact with the trench; and a re-crystallization layer formed in the substrate to be in contact with bottom and side surfaces of the trench and a surface of the substrate. The re-crystallization layer may contain one or more kinds of elements different from an element constituting the substrate.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Byoung-Gyu Kim
  • Patent number: 10431471
    Abstract: Various embodiments provide a method of planarizing a semiconductor wafer, wherein the method comprises providing a semiconductor wafer comprising a surface; and forming a mask layer on the surface of the semiconductor wafer, wherein a thickness of the mask layer is smaller in thinning areas, which are to be thinned for planarizing, than in areas which are not to be thinned for planarizing.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: Carsten Von Koblinski, Markus Ottowitz, Andreas Riegler
  • Patent number: 10364145
    Abstract: A roughened silicon surface is formed by a process including repetitively performed roughening cycles. Each roughening cycles including a step for depositing a non-planar polymeric layer over an area of a silicon body and a step for plasma etching the polymeric layer and the area of the silicon body etch in a non-unidirectional way. As a result, a surface portion of the silicon body is removed, in a non-uniform way, to a depth not greater than 10 nm.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Somaschini, Pietro Petruzza
  • Patent number: 10262870
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 10141507
    Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 10134947
    Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 20, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chia Chen Tsai, Chen Ou, Chi Ling Lee, Chi Shiang Hsu
  • Patent number: 10115628
    Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: forming a dielectric layer on a semiconductor substrate; forming a functional layer on the dielectric layer; forming a hard mask layer on the functional layer; patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer, the functional layer and extends into the dielectric layer; performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; performing a first process on the semiconductor substrate to remove a portion of the dielectric layer underneath the opening to expose the semiconductor substrate; and removing the oxide layers on the side surfaces of the functional layer to form a contact hole. The contact hole has a wider opening in the upper part than in the lower part.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 30, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Shimin Peng
  • Patent number: 10072351
    Abstract: Semi-conductor wafers with thin and thicker regions at controlled locations may be for Photovoltaics. The interior may be less than 180 microns or thinner, to 50 microns, with a thicker portion, at 180-250 microns. Thin wafers have higher efficiency. A thicker perimeter provides handling strength. Thicker stripes, landings and islands are for metallization coupling. Wafers may be made directly from a melt upon a template with regions of different heat extraction propensity arranged to correspond to locations of relative thicknesses. Interstitial oxygen is less than 6×1017 atoms/cc, preferably less than 2×1017, total oxygen less than 8.75×1017 atoms/cc, preferably less than 5.25×1017. Thicker regions form adjacent template regions having relatively higher heat extraction propensity; thinner regions adjacent regions with lesser extraction propensity. Thicker template regions have higher extraction propensity. Functional materials upon the template also have differing extraction propensities.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 11, 2018
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Ralf Jonczyk, Adam L. Lorenz, Richard L. Wallace, G. D. Stephen Hudelson
  • Patent number: 9985094
    Abstract: A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 9966273
    Abstract: There is provided a plasma etching method. The plasma etching method includes generating plasma, by using a first high frequency power output from a first high frequency power supply, from a first processing gas that contains fluorine-containing gas, thereby etching a laminated film of a silicon oxide film and a silicon nitride film through the generated plasma, and generating plasma, by using the first high frequency power, from a second processing gas that contains bromine-containing gas, thereby etching the laminated film through the generated plasma.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 8, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Takayama, Sho Tominaga, Yoshiki Igarashi
  • Patent number: 9881107
    Abstract: A simulation method includes acquiring a processing condition for performing predetermined processing on a processing target with use of plasma, calculating a solid angle corresponding to a field-of-view region through which plasma space is viewable from a predetermined evaluation point in the predetermined evaluation point on a surface of the processing target based on the processing condition, and calculating an incident radical amount entering the evaluation point by a flux method with use of a function which takes a reaction probability between the solid angle and the evaluation point of a radical entering the evaluation point as an argument.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: January 30, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Nobuyuki Kuboi, Takashi Kinoshita
  • Patent number: 9881809
    Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: January 30, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Xin-Guan Lin, Hong-Ji Lee
  • Patent number: 9865471
    Abstract: A method for etching a silicon film formed on a substrate includes supplying HBr gas, NF3 gas, and O2 gas into a chamber and performing a plurality of etching processes on the silicon film with a plasma generated by the supplied HBr gas, NF3 gas, and O2 gas, gradually reducing a flow rate of the HBr gas during the plurality of etching processes, and adjusting a flow rate of the O2 gas according to the reduction of the HBr gas.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Gaku Shimoda, Hotaka Maruyama, Takanori Sato, Masafumi Urakawa, Masahiro Ogasawara
  • Patent number: 9865499
    Abstract: A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a second surface of a substrate by supplying the silicon-containing gas to the substrate. A silicon component contained in the silicon-containing gas adsorbed on the first surface of the depression is partially etched by supplying an etching gas to the substrate. A silicon-containing film is deposited in the depression by supplying a reaction gas reactable with the silicon component to the substrate so as to produce a reaction product by causing the reaction gas to react with the silicon component left in the depression without being etched.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 9, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Jun Sato, Hiroyuki Kikuchi, Masahiro Murata, Shigehiro Miura
  • Patent number: 9825116
    Abstract: A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 21, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, Melanie S. Yajima
  • Patent number: 9805954
    Abstract: A manufacturing method forms an oxide insulating layer and a first plasma etching treatment forms a depressed portion therein. A second plasma etching treatment forms a trench including curved lower corner portions. An oxide semiconductor film is formed in contact with a bottom portion, the curved lower corner portions, and side portions of the trench. Source and electrodes are formed to be electrically connected to the oxide semiconductor film. A gate insulating layer is formed over the oxide semiconductor film and a gate electrode is formed over the gate insulating layer. The first plasma etching treatment is performed with a first bias power and a first power of a first power source, and the second plasma etching treatment is performed with a second bias power and a second power of a second power source, wherein the second bias power is lower than the first bias power.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa
  • Patent number: 9754779
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa
  • Patent number: 9748306
    Abstract: Radiation detectors are disclosed. The radiation detectors comprise a substrate and at least one radiation sensitive region on the substrate, the at least one radiation sensitive region comprising an array of elongate nanostructures projecting from the substrate. Methods of manufacture of such radiation detectors are also disclosed.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: August 29, 2017
    Assignee: BAE SYSTEMS plc
    Inventor: Russell Alan Morgan
  • Patent number: 9716195
    Abstract: A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Richard A. Haight, Jeehwan Kim, Yun Seog Lee
  • Patent number: 9659849
    Abstract: A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 23, 2017
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigeki Chujo, Koichi Nakayama
  • Patent number: 9530666
    Abstract: A plasma etching method includes a first process and a second process. In the first process, a hole is formed in a processing target film formed on a substrate accommodated within a processing chamber by performing an etching process of etching the processing target film. In the second process, a removing process, a deposition process and an extending process are repeatedly performed. In the removing process, a reaction product adhering to an inlet portion of the hole which is formed through the etching process is removed. In the deposition process, a deposit is deposited on a sidewall of the hole from which the reaction product is removed through the removing process. In the extending process, the hole, in which the deposit is deposited on the sidewall thereof through the deposition process, is deeply etched by performing the etching process.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hideki Mizuno, Kumiko Yamazaki
  • Patent number: 9502258
    Abstract: A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single material made from, for example, a silicon-containing material or a metal-containing material. The method includes directionally ion-implanting the patterned structure to implant the bottom of the gap without implanting substantially the walls of the gap. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that either (1) the walls are selectively etched relative to the floor of the gap, or (2) the floor is selectively etched relative to the walls of the gap. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 22, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Jun Xue, Ching-Mei Hsu, Zihui Li, Ludovic Godet, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9496148
    Abstract: A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p? layer and an n+ layer. Both p? and n+ layers have exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge. The method includes controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer edge, and reactive ion etching the n+ layer while controlling the charge flow along the edge of the n+ layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sunit S. Mahajan, Bachir Dirahoui, Richard Wise
  • Patent number: 9466495
    Abstract: Systems and methods are provided for fabricating semiconductor devices. For example, a substrate is provided. A polymer layer is formed on the substrate. An oxygen-based plasma is applied to remove the polymer layer. An oxidizing solution is applied to generate a dielectric layer. A conductive layer is formed on the dielectric layer.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Shao-Jyun Wu
  • Patent number: 9400429
    Abstract: A composition for forming a resist underlayer film is provided, which contains: a calixarene-based compound obtained from a calixarene by substituting at least a part of hydrogen atoms each on phenolic hydroxyl groups comprised in the calixarene, with a monovalent organic group having 1 to 30 carbon atoms; and an organic solvent. The monovalent organic group preferably includes a crosslinkable group. A part of hydrogen atoms each on phenolic hydroxyl groups of the calixarene-based compound is preferably substituted. The ratio of the number of substituted phenolic hydroxyl groups to the number of unsubstituted phenolic hydroxyl groups in the calixarene-based compound is preferably no less than 30/70 and no greater than 99/1.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 26, 2016
    Assignee: JSR CORPORATION
    Inventors: Fumihiro Toyokawa, Shin-ya Nakafuji, Gouji Wakamatsu
  • Patent number: 9397100
    Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Manoj Mehrotra, Mahalingam Nandakumar
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Patent number: 9023693
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Patent number: 9023669
    Abstract: A processing method of a silicon substrate including forming a second opening in a bottom portion of a first opening using a patterning mask having a pattern opening by plasma reactive ion etching. The reactive ion etching is performed with a shield structure formed in or on the silicon substrate, the shield structure preventing inside of the first opening from being exposed to the plasma.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: May 5, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsushi Hiramoto, Masahiko Kubota, Ryoji Kanri, Akihiko Okano, Yoshiyuki Fukumoto, Atsunori Terasaki
  • Patent number: 9018102
    Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohammed Radwan, Matthias Zinke
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Patent number: 8994177
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8986560
    Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8981441
    Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
  • Patent number: 8969210
    Abstract: There is provided a plasma etching apparatus provided for performing an etching in a desirable shape. The plasma etching apparatus includes a processing chamber 12 for performing a plasma process on a target substrate W; a gas supply unit 13 for supplying a plasma processing gas into the processing chamber 12; a supporting table positioned within the processing chamber 12 and configured to support the target substrate thereon; a microwave generator 15 for generating a microwave for plasma excitation; a plasma generation unit for generating plasma within the processing chamber 12 by using the generated microwave; a pressure control unit for controlling a pressure within the processing chamber 12; a bias power supply unit for supplying AC bias power to the supporting table 14; and a control unit for controlling the AC bias power by alternately repeating supply and stop of the AC bias power.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Toshihisa Nozawa, Masaru Sasaki, Jun Hashimoto, Shota Yoshimura, Toshihisa Ozu, Tetsuya Nishizuka
  • Patent number: 8936948
    Abstract: A hard mask, a protective film, which protects the hard mask film from oxidation, a first mask film and a first organic film are sequentially stacked. The first organic film is processed into a first pattern, and the first mask film is etched using the patterned first organic film as a mask. After the first organic film is removed, a second organic film is formed. The second organic film is processed into a second pattern. The first mask film is secondary etched using the patterned second organic film as a mask so that the surface of the first mask film is exposed but the surface of the protective film is not exposed, thereby selectively patterning only the first mask film. After that, when removing the residual second organic film by ashing, it is possible to ensure the function of the protective film that protects the hard mask film from oxidation.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Osamu Fujita
  • Patent number: 8932947
    Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Joo Won Han, Kee Young Cho, Han Soo Cho, Sang Wook Kim, Anisul H. Khan
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8912098
    Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 8906810
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Patent number: 8900403
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho
  • Patent number: 8900402
    Abstract: A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho