Chemical Or Electrical Treatment, E.g., Electrolytic Etching (epo) Patents (Class 257/E21.215)
  • Patent number: 10262853
    Abstract: The invention is directed to a method for removing particulate contaminants from the backside of a wafer or reticle, and to a cleaning substrate for use in such method. In the method of the invention particulate contaminants are removed from the backside of a wafer or reticle with a cleaning substrate. The cleaning substrate comprises protrusions and a tacky layer between the protrusions. The method comprises contacting the backside of the wafer or reticle with the protrusions of the cleaning substrate while maintaining a distance between the wafer or reticle and the tacky layer, the distance being in the range of 1-10 ?m.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 16, 2019
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO
    Inventors: Sjoerd Oostrom, Jacques Cor Johan Van Der Donck, Olaf Kievit, Nicole Ellen Papen-Botterhuis
  • Patent number: 10050122
    Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hidekazu Oda
  • Patent number: 9997705
    Abstract: A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 12, 2018
    Assignee: William Marsh Rice University
    Inventors: James M. Tour, Gunuk Wang, Yang Yang, Yongsung Ji
  • Patent number: 9504162
    Abstract: Certain processes for manufacturing an electrochemical sensor module include etching a Silicon wafer to form precursor sensor bodies, disposing sensor fibers along rows of the precursor sensor bodies, securing a rigid layer over the sensor fibers, dividing the wafer, rigid layer, and sensor fibers into individual precursor sensor bodies, and joining each precursor sensor body to a component body to form sensor modules.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 22, 2016
    Assignee: PEPEX BIOMEDICAL, INC.
    Inventor: James L. Say
  • Patent number: 8999744
    Abstract: Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: April 7, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Ran Park, O-Kyun Kwon
  • Patent number: 8940640
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Xiao
  • Patent number: 8900399
    Abstract: An anodic etching system for simultaneously etching a multiplicity of substrates comprises: an etching tank for containing therein an etchant solution; a power supply connected between a first electrode and a second electrode, the first electrode and the second electrode being immersible in the etchant solution and positioned at opposite ends of the tank; and a plurality of support plates serially arranged between the first electrode and the second electrode and sealed to walls of the tank, wherein each of the plurality of support plates is configured to support at least one of the multiplicity of substrates, and wherein any consecutive pair of the plurality of support plates defines an isolated volume of the tank for containing a portion of the etchant solution. The plurality of support plates may be susceptors configured for holding the multiplicity of substrates in a chemical vapor deposition tool.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 2, 2014
    Assignee: Crystal Solar, Inc.
    Inventors: Tirunelveli S. Ravi, Ananda H. Kumar, Ashish Asthana, Kyle Ross Tantiwong, Visweswaren Sivaramakrishnan
  • Patent number: 8894803
    Abstract: A process for etching the surfaces of semiconductor substrates utilizes a texturing tank which introduces a process fluid through a circulating system. The process fluid is heated to a desired temperature and maintained at a desired concentration prior to entering a processing area where laminar flow is produced to more quickly and uniformly roughen the surface of semiconductor substrates. The texturing tank permits removal of bubbles and eliminates temperature stratification in the processing area.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 25, 2014
    Assignee: Heateflex Corporation
    Inventors: Jorge Ramirez, Hector Joel Castaneda, Melissa A. Tiongco
  • Patent number: 8895342
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)yAl1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Patent number: 8852447
    Abstract: A method for simultaneously detecting and separating a target analyte such as a protein or other macromolecule that includes providing a porous silicon matrix on the silicon substrate, exposing the porous silicon matrix to an environment suspect of containing the target analyte, observing optical reflectivity of the porous silicon matrix; and correlating the changes in the silicon substrate to the target analyte.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 7, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael J. Sailor, Gaurav Abbi, Boyce E. Collins, Keiki-Pua S. Dancil
  • Patent number: 8853091
    Abstract: A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: October 7, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Justin H. Sato, Brian Hennes, Greg Stom, Robert P. Ma, Walter E. Lundy
  • Patent number: 8845916
    Abstract: A method for manufacturing a glass plate using laser etching includes a dipping step for dipping a glass plate, which will be etched, into an etching solution, a patterning step for irradiating laser to the glass plate dipped in the etching solution to form a pattern therein, and a washing step for washing the patterned glass plate. This method allows making a plate with a high aspect ratio and fine line widths in comparison to a conventional plate manufacturing method using photoresist for etching, and also ensures more efficient energy consumption and higher etching efficiency rather than an etching method using laser only.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 30, 2014
    Assignee: LG Chem, Ltd.
    Inventor: Bu-Gon Shin
  • Patent number: 8828878
    Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
  • Patent number: 8815632
    Abstract: A method of manufacturing an order vacancy compound (OVC) is provided. The method includes the following steps. A trivalent ion, a hexavalent ion and one of a univalent ion and a bivalent ion for an electrodeposition process are provided to form a solar energy absorbing film. The OVC is formed by performing an electrochemical etching process on the solar energy absorbing film.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 26, 2014
    Assignee: National Chen-Kung University
    Inventor: Wen-Hsi Lee
  • Patent number: 8809980
    Abstract: An infrared sensor according to the present invention includes a semiconductor substrate, a thin-film pyroelectric element made of lead titanate zirconate and disposed on the semiconductor substrate, a coating film coating the pyroelectric element and having a topmost surface that forms a light receiving surface for infrared rays, and a cavity formed to a shape dug in from a top surface of the semiconductor substrate at a portion opposite to the pyroelectric element and thermally isolates the pyroelectric element from the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Goro Nakatani
  • Patent number: 8790953
    Abstract: The surface of silicon is textured to create black silicon on a nano-micro scale by electrochemical reduction of a silica layer on silicon in molten salts. The silica layer can be a coating, or a layer caused by the oxidation of the silicon.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 29, 2014
    Inventors: Derek John Fray, Eimutis Juzeliunas
  • Patent number: 8786094
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Wen-Hao Chen, Dian-Hau Chen
  • Patent number: 8729658
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Publication number: 20140113452
    Abstract: A wafer edge trimming method comprises steps as follows: Firstly, an etch-resistant layer is formed on a surface of a wafer. A wet treatment process is then performed to remove a portion of the etch-resistant layer, so as to expose a portion of the surface adjacent to an edge of the wafer. Subsequently, an etching process is performed to remove a portion of the wafer that is not covered by the remained etch-resistant layer.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu LIN, Chung-Sung CHANG, Chun-Hung CHEN, Ming-Tse LIN, Yung-Chang LIN
  • Publication number: 20140042562
    Abstract: A device includes a Micro-Electro-Mechanical System (MEMS) wafer having a MEMS device therein. The MEMS device includes a movable element, and first openings in the MEMS wafer. The movable element is disposed in the first openings. A carrier wafer is bonded to the MEMS wafer. The carrier wafer includes a second opening connected to the first openings, wherein the second opening includes an entry portion extending from a surface of the carrier wafer into the carrier wafer, and an inner portion wider than the entry portion, wherein the inner portion is deeper in the carrier wafer than the entry portion.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Te-Hao Lee, Chung-Hsien Lin
  • Patent number: 8648353
    Abstract: Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: February 11, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara
  • Publication number: 20140024219
    Abstract: At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ryan O. Jung, Sivananda K. Kanakasabapathy, Yunpeng Yin
  • Publication number: 20140008756
    Abstract: A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chengwen Pei, Gan Wang
  • Patent number: 8623769
    Abstract: A through hole forming method includes forming a plurality of small holes in a first substrate surface of a substrate including the first substrate surface and a second substrate surface as a back surface of the first substrate surface, forming a thermally oxidized film by thermally oxidizing partition walls between the adjacent small holes and bottoms of the small holes, and removing the thermally oxidized film.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 7, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Miho Shiraki, Junichi Takeuchi
  • Publication number: 20140001638
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Min Fu, Wen-Hao Chen, Dian-Hau Chen
  • Publication number: 20130334594
    Abstract: Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Inventors: Jerome A. Imonigie, Patrick M. Flynn, Sandra L. Tagg, Prashant Raghu
  • Publication number: 20130316538
    Abstract: The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Augustin J. Hong, Ning Li, Devendra K. Sadana, Katherine L. Saenger, Davood Shahrjerdi, Kuen-Ting Shiu
  • Patent number: 8546269
    Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Guy Cohen, Lidija Sekaric, Jeffrey Sleight
  • Publication number: 20130252355
    Abstract: A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an emission spectrum of a compound generated from the patterning step. The compound includes an element in the patterned layer. At a time the signal strength is reduced to a pre-determined threshold value, the patterning step is stopped.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Szu-Hung Yang, Chiung Wen Hsu
  • Patent number: 8530354
    Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 10, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Publication number: 20130221448
    Abstract: A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Chang, Chih-Fang Liu, Chih-Tang Peng, Tai-Chun Huang, Ryan Chia-Jen Chen
  • Patent number: 8513129
    Abstract: Methods for manufacturing a semiconductor device are provided. In one embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and has a first set of interconnect features. The first film stack comprises a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer. The first photoresist layer is patterned by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: August 20, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Martin Jay Seamons, Kwangduk Douglas Lee, Chiu Chan, Patrick Reilly, Sudha Rathi
  • Publication number: 20130210237
    Abstract: A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: United Microelectronics Corp.
    Inventors: Hung-Yi Wu, Yuan-Chi Pai, Yu-Wei Cheng, Chang-Mao Wang
  • Patent number: 8509277
    Abstract: A multiwavelength optical device includes a substrate; a first mirror section including a plurality of first mirror layers stacked on the substrate; an active layer stacked on the first mirror section, the active layer including a light emission portion; a second mirror section including a plurality of second mirror layers stacked on the active layer; a first electrode disposed between the active layer and the second mirror section; and a second electrode disposed between the first mirror section and the active layer.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshikazu Hattori
  • Publication number: 20130203255
    Abstract: A method for reducing contamination in an etch chamber is provided. A substrate with a metal containing layer is placed in the etch chamber. The metal containing layer is etched, producing nonvolatile metal residue deposits on surfaces of the etch chamber, wherein some of the metal residue of the metal residue deposits is in a first state. The substrate is removed from the etch chamber. The chamber is conditioned by converting metal residue in the first state to metal residue in a second state, where metal residue in the second state has stronger adhesion to surfaces of the etch chamber than metal residue in the first state.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 8, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Joydeep GUHA, Sanket SANT, Butsurin JINNAI
  • Patent number: 8501611
    Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
  • Patent number: 8481435
    Abstract: The present invention relates to a process for preparing a functionalized Si/Ge-surface, wherein an unfunctionalised Si/Ge-surface is contacted in the presence of ultraviolet radiation with a C2-C50 alkene and/or a C2-C50 alkyne, the alkene and/or alkyne being optionally substituted and/or being optionally interrupted by one or more heteroatoms. The present invention further relates to articles or substrates comprising the functionalized Si/Ge-surface and the use of the functionalised Si/Ge-surface to prevent or to reduce adsorption of a biomolecule to an article or a substrate.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 9, 2013
    Assignee: Wageningen University
    Inventors: Catharina Gerarda Petronella Henrica Schroën, Michel Rosso, Johannes Teunis Zuilhof
  • Publication number: 20130167632
    Abstract: A microelectromechanical system device including anchors and mass is provided. Electrical interconnections are formed on the mass by using a insulation layer of mass, an electrical insulation trench and conductive through hole. The electrical interconnections replace the cross-line structure without adding additional processing steps, thereby reducing the use of the conductive layer and the electrical insulation layer. A method for fabricating the microelectromechanical system device is also provided.
    Type: Application
    Filed: April 30, 2012
    Publication date: July 4, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Ta Huang, Yu-Wen Hsu, Chin-Fu Kuo
  • Patent number: 8455286
    Abstract: A method of forming a MEMS device includes forming a sacrificial layer over a substrate. The method further includes forming a metal layer over the sacrificial layer and forming a protection layer overlying the metal layer. The method further includes etching the protection layer and the metal layer to form a structure having a remaining portion of the protection layer formed over a remaining portion of the metal layer. The method further includes etching the sacrificial layer to form a movable portion of the MEMS device, wherein the remaining portion of the protection layer protects the remaining portion of the metal layer during the etching of the sacrificial layer to form the movable portion of the MEMS device.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: June 4, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lisa H. Karlin, David W. Kierst, Lianjun Liu, Wei Liu, Ruben B. Montez, Robert F. Steimle
  • Publication number: 20130130416
    Abstract: A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.
    Type: Application
    Filed: February 13, 2012
    Publication date: May 23, 2013
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 8445385
    Abstract: Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a masking layer, patterning the masking layer, and etching the CNT film through the patterned masking layer using a non-oxygen based chemistry. Other aspects are also described.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: May 21, 2013
    Assignee: SanDisk 3D LLC
    Inventors: April D. Schricker, Andy Fu, Michael Konevecki, Steven Maxwell
  • Publication number: 20130120505
    Abstract: A print head including a jet stack can be formed using semiconductor device manufacturing techniques. A blanket metal layer, a blanket piezoelectric element layer, and a blanket conductive layer can be formed over a semiconductor substrate such as a semiconductor wafer or wafer section. The piezoelectric element layer and the blanket conductive layer can be patterned to provide a plurality of transducer piezoelectric elements and top electrodes respectively, while the metal layer forms a bottom electrode for the plurality of transducers. Subsequently, the semiconductor substrate can be patterned to form a body plate for the print head jet stack. Forming a print head jet stack using semiconductor device manufacturing techniques can provide a high resolution device with small feature sizes.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: Xerox Corporation
    Inventors: Peter J. Nystrom, Bijoyraj Sahu
  • Publication number: 20130122706
    Abstract: According to one embodiment, a method of manufacturing of a semiconductor device is provided. In the method, a front surface of a semiconductor substrate and a front surface of a support substrate are bonded to each other by an adhesive. A part of a circumferential part of the support substrate is subjected to water-repellent treatment to thereby form a water-repellent area on the part of the circumferential part in such a manner that the water-repellent area and an end face of the adhesive are in contact with each other. The semiconductor substrate is removed from a rear surface side by wet etching.
    Type: Application
    Filed: March 23, 2012
    Publication date: May 16, 2013
    Inventors: Hisashi OKUCHI, Hidekazu Hayashi, Kentaro Shimayama, Hiroshi Tomita
  • Patent number: 8426235
    Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: April 23, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chienliu Chang
  • Patent number: 8426257
    Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Sik Park, Hae-Jung Lee, Jae-Kyun Lee
  • Publication number: 20130078810
    Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-I Lee, Huang Soon Kang, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8405185
    Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
  • Patent number: 8399356
    Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: March 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoya Sakamoto, Takahiro Sato, Yoshiaki Oikawa, Rai Sato, Yamato Aihara, Takayuki Cho, Masami Jintyou
  • Patent number: 8399359
    Abstract: A manufacturing method for a dual damascene structure includes providing a substrate having a dielectric layer, a first hard mask layer and a second hard mask layer sequentially formed thereon, performing a first double patterning process to sequentially form a plurality of first trench openings and a plurality of second trench openings in the second hard mask layer, performing a second double patterning process to sequentially form a plurality of first via openings and a plurality of second via openings in the fist hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 19, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shougang Mi, Duan Quan Liao
  • Publication number: 20130062713
    Abstract: [Subject] To provide a pressure sensor capable of implementing cost reduction and miniaturization. [Solving Means] A pressure sensor 1 includes a silicon substrate 2 provided therein with a reference pressure chamber 8, a diaphragm 10, consisting of part of the silicon substrate 2, formed on a surface layer portion of the silicon substrate 2 to partition a reference pressure chamber 8, and an etching stop layer 9 formed on a lower surface of the diaphragm 10 facing the reference pressure chamber 8. A through-hole 11 communicating with the reference pressure chamber 8 is formed on the diaphragm 10, and a filler 13 is arranged in the through-hole 11.
    Type: Application
    Filed: May 25, 2011
    Publication date: March 14, 2013
    Applicant: ROHM CO., LTD.
    Inventors: Masahiro Sakuragi, Toma Fujita, Mizuho Okada