Abstract: A plasma processing method in which performing a plasma etching on metal layers formed on a substrate is conducted to form a pattern having the metal layers in a stacked structure, and then a deposit containing a metal that forms the metal layers and being deposited on a sidewall portion of the pattern is removed, the method includes: forming a protective layer by forming an oxide or chloride of the metal on sidewall portions of the metal layers; removing the deposit by applying a plasma of a gas containing fluorine atoms; and reducing the oxide or chloride of the metal by applying a plasma containing hydrogen after forming the protective layer and removing the deposit.

Abstract: Methods of decreasing the effective dielectric constant present between two conducting components of an integrated circuit are described. The methods involve the use of a gas phase etch which is selective towards the oxygen-rich portion of the low-K dielectric layer. The etch rate attenuates as the etch process passes through the relatively high-K oxygen-rich portion and reaches the low-K portion. The etch process may be easily timed since the gas phase etch process does not readily remove the desirable low-K portion.

Abstract: The present invention intends to provide a surface-emitting laser light source using a two-dimensional photonic crystal in which the efficiency of extracting light in a direction perpendicular to the surface is high. In a laser light source provided with a two-dimensional photonic crystal layer created from a plate-shaped matrix body in which a large number of holes are periodically arranged and an active layer arranged on one side of the two-dimensional photonic crystal layer, the holes are created to be columnar with a predetermined cross-sectional shape such as a circular shape, and the main axis of each of the columnar holes is tilted to a surface of the matrix body. When provided with this two-dimensional photonic crystal layer, the surface-emitting laser source using a two-dimensional photonic crystal has a Q? value (i.e.

Abstract: A movable ground ring of a movable substrate support assembly is described. The movable ground ring is configured to fit around and provide an RF return path to a fixed ground ring of the movable substrate support assembly in an adjustable gap capacitively-coupled plasma processing chamber wherein a semiconductor substrate supported in the substrate support assembly undergoes plasma processing.

Abstract: Line-wiggling and striation caused by collapse of a pattern after a silicon dioxide film is etched by plasma with the use of a multilayer resist mask are prevented or suppressed. In a plasma etching method of etching a film to be etched by plasma with the use of a multilayer resist mask, the multilayer resist mask includes an upper layer resist, an inorganic intermediate film, and a lower layer resist, and the method includes a side wall protective film forming step of forming a side wall protective film on a side wall of the lower layer resist.

Abstract: A plasma processing method of subjecting a substance to plasma processing by using a semiconductor device manufacturing apparatus including a process chamber, a unit for supplying gas to the process chamber, an exhausting unit to reduce pressure in the process chamber, a high frequency power source for plasma generation, a coil for generating a magnetic field, and a mounted electrode for mounting the substance to be processed. The method includes steps of subjecting the substance to a predetermined plasma processing, changing the magnetic field distribution, so as to make a plasma distribution of the process chamber with respect to the surface of the substance to be processed, in a convex form, at a time of igniting the plasma and after completion of the predetermined plasma processing, as compared with a plasma distribution with respect to the surface of the substance to be processed during the predetermined plasma processing.

Abstract: Provided is a method of setting a thickness of a dielectric, which restrains the dielectric formed in an electrode from being consumed when etching a silicon dioxide film on a substrate by using plasma. In a substrate processing apparatus including an upper electrode facing a susceptor and the dielectric formed of silicon dioxide in the upper electrode, a silicon dioxide film formed on a wafer being etched by using plasma, an electric potential of the plasma facing the dielectric in a case where the dielectric is not formed in the upper electrode is estimated based on a bias power applied to the susceptor and an A/C ratio in a chamber, and the thickness of the dielectric is determined so that an electric potential of the plasma, which is obtained by multiplying the estimated electric potential of the plasma by a capacity reduction coefficient calculated when a capacity of the dielectric and a capacity of a sheath generated around a surface of the dielectric are combined, is 100 eV or less.

Abstract: A TeraMOS sensor based on a CMOS-SOI-MEMS transistor, thermally isolated by the MEMS post-processing, designed specifically for the detection of THz radiation which may be directly integrated with the CMOS-SOI readout circuitry, in order to achieve a breakthrough in performance and cost. The TeraMOS sensor provides a low-cost, high performance THz passive or active imaging system (roughly in the range of 0.5-1.5 THz) by combining several leading technologies: Complementary Metal Oxide Semiconductor (CMOS)-Silicon on Insulator (SOI), Micro Electro Mechanical Systems (MEMS) and photonics. An array of TeraMOS sensors, integrated with readout circuitry and driving and supporting circuitry provides a monolithic focal plane array or imager. This imager is designed in a commercial CMOS-SOI Fab and the MEMS micromachining is provided as post-processing step in order to reduce cost.

Abstract: A substrate processing apparatus includes a chamber accommodating a wafer, a susceptor disposed inside the chamber and on which the wafer is held, an upper electrode facing the susceptor, and a second high frequency power source connected to the susceptor, wherein the upper electrode is electrically connected to a ground and is moveable with respect to the susceptor. The substrate processing apparatus divides a potential difference between plasma generated in a processing space and the ground into a potential difference between the plasma and a dielectric and a potential difference between the dielectric and the ground by burying the dielectric in the upper electrode, and changes a gap between the upper electrode and the susceptor.

Abstract: There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: (3b) etching a substrate by positive ions in plasma by applying both the plasma RF and the bias RF; (3c) generating negative ions in a processing chamber by stopping the application of both the plasma RF and the bias RF; and (3a) attracting the negative ions to the substrate by applying the bias RF and stopping the application of the plasma RF. A duty ratio of the bias RF is set to be greater than a duty ratio of the plasma RF.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: A plasma processing apparatus, comprising: a reaction chamber; a plurality of discharge portions each made up of a pair of a first electrode and a second electrode disposed inside the reaction chamber so as to oppose to each other and to cause a plasma discharge under an atmosphere of a reactant gas; and a dummy electrode, wherein a plurality of the first electrodes are connected to a power supply portion, a plurality of the second electrodes are grounded, and the dummy electrode is disposed so as to oppose to an outer surface side of an external first electrode in terms of a parallel direction out of the plurality of the first electrodes which are disposed in the parallel direction, and is grounded.

Abstract: Methods of processing substrates having metal layers are provided herein. In some embodiments, a method of processing a substrate comprising a metal layer having a patterned mask layer disposed above the metal layer, the method may include etching the metal layer through the patterned mask layer; and removing the patterned mask layer using a first plasma formed from a first process gas comprising oxygen (O2) and a carbohydrate. In some embodiments, a two step method with an additional second process gas comprising chlorine (Cl2) or a sulfur (S) containing gas, may provide an efficient way to remove patterned mask residue.

Abstract: A method of patterning an insulation layer is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a cap layer, a SiCOH-containing layer overlying the cap layer, and a hard mask overlying the SiCOH-containing layer. The method further includes transferring a pattern through the film stack by performing a series of etch processes in a plasma etching system, wherein the series of etch processes utilize a temperature controlled substrate holder in the plasma etching system according to a substrate temperature control scheme that achieves etch selectivity between the SiCOH-containing layer and the underlying cap layer.

Abstract: The present invention relates to a method of semiconductor wafer back processing, which includes applying a radiation-curable pressure-sensitive adhesive sheet comprising a base film and a pressure-sensitive adhesive layer disposed on one side of the base film to a front side of a semiconductor wafer, the front side of the semiconductor wafer having recesses and protrusions; grinding the back side of the semiconductor wafer in such a state that the radiation-curable pressure-sensitive adhesive sheet is adherent to the front side of the semiconductor; and irradiating the pressure-sensitive adhesive sheet with a radiation to thereby cure the pressure-sensitive adhesive layer, followed by subjecting said ground back side of the semiconductor wafer to a surface treatment; and a radiation-curable pressure-sensitive adhesive sheet for use in the method of semiconductor wafer back processing.

Abstract: In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.

Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

Abstract: A method for removing silicon oxide based residue from a stack with a doped silicon oxide layer with features with diameters less than 100 nm is provided. A wet clean solution of between 25% to 60% by weight of NH4F, and between 0.05% and 5% by weight of phosphoric acid, and between 0.05% and 5% by weight citric acid, in a water solvent is provided to an area on a surface of the stack. The wet clean solution is removed from the area on the surface of the stack between 0.5 to 10 seconds after the area on the surface of the stack was exposed to the wet clean solution.

Abstract: A method of etching patterned heterogeneous silicon-containing structures is described and includes a remote plasma etch with inverted selectivity compared to existing remote plasma etches. The methods may be used to conformally trim polysilicon while removing little or no silicon oxide. More generally, silicon-containing films containing less oxygen are removed more rapidly than silicon-containing films which contain more oxygen. Other exemplary applications include trimming silicon carbon nitride films while essentially retaining silicon oxycarbide. Applications such as these are enabled by the methods presented herein and enable new process flows. These process flows are expected to become desirable for a variety of finer linewidth structures. Methods contained herein may also be used to etch silicon-containing films faster than nitrogen-and-silicon containing films having a greater concentration of nitrogen.

Abstract: The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm2 to 1 MW/cm2 for a short time of 0.

Abstract: A plasma processing apparatus and a method of manufacturing a semiconductor device which can prevent a discharge from occurring between a substrate such as a semiconductor wafer or the like, and a base material of a lower electrode or a peripheral structure of the base material, and can improve yield and productivity. The plasma processing apparatus includes a processing chamber, a lower electrode, an upper electrode, and a plurality of lifter pins for supporting a substrate to be processed. Each of the lifter pins includes a pin body part and a lid part which is disposed on a top portion of the pin body part and has an outer diameter greater than an outer diameter of the pin body part.

Abstract: A movable symmetric chamber liner in a plasma reaction chamber, for protecting the plasma reaction chamber, enhancing the plasma density and uniformity, and reducing process gas consumption, comprising a cylindrical wall, a bottom wall with a plurality of openings, a raised inner rim with an embedded heater, heater contacts, and RF ground return contacts. The chamber liner is moved by actuators between an upper position at which substrates can be transferred into and out of the chamber, and a lower position at which substrate are processed in the chamber. The actuators also provide electrical connection to the heater and RF ground return contacts.

Abstract: The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.

Abstract: Provided are a cleaning composition which is capable of inhibiting the metal of a semiconductor substrate from corrosion, and has an excellent removability of plasma etching residues and/or ashing residues on the semiconductor substrate, a method for producing a semiconductor device, and a cleaning method using the cleaning composition. The cleaning composition for removing plasma etching residues and/or ashing residues formed on a semiconductor substrate, and a preparation method and a cleaning method for a semiconductor device, using the cleaning composition, wherein the cleaning composition includes (Component a) water; (Component b) an amine compound; (Component c) hydroxylamine and/or a salt thereof; (Component d) a quaternary ammonium compound; (Component e) an organic acid; and (Component f) a water-soluble organic solvent; and has a pH of 6 to 9.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump exhausts the chamber. The radio frequency power supply supplies radio frequency power to the electrode through the conductive knitted wire mesh.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: The present invention is directed to a method and apparatus for etching various metals that may be used in semiconductor or integrated circuit processing through the use of non-halogen gases such as hydrogen, helium, or combinations of hydrogen and helium with other gases such as argon. In one exemplary embodiment of the present invention, in a reaction chamber, a substrate having a metal interconnect layer deposited thereon is exposed to a plasma formed of non-halogen gas. The plasma generated is maintained for a certain period of time to provide for a desired or expected etching of the metal. In some embodiments, the metal interconnect layer may be copper, gold or silver.

Abstract: A method of bevel edge processing a semiconductor in a bevel plasma processing chamber in which the semiconductor substrate is supported on a semiconductor substrate support is provided. The method comprises evacuating the bevel etcher to a pressure of 3 to 100 Torr and maintaining RF voltage under a threshold value; flowing a process gas into the bevel plasma processing chamber; energizing the process gas into a plasma at a periphery of the semiconductor substrate; and bevel processing the semiconductor substrate with the plasma.

Abstract: In a method of making a polymer structure on a substrate a layer of a first polymer, having a horizontal top surface, is applied to a surface of the substrate. An area of the top surface of the polymer is manipulated to create an uneven feature that is plasma etched to remove a first portion from the layer of the first polymer thereby leaving the polymer structure extending therefrom. A light emitting structure includes a conductive substrate from which an elongated nanostructure of a first polymer extends. A second polymer coating is disposed about the nanostructure and includes a second polymer, which includes a material such that a band gap exists between the second polymer coating and the elongated nanostructure. A conductive material coats the second polymer coating. The light emitting structure emits light when a voltage is applied between the conductive substrate and the conductive coating.

Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate.

Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.

Abstract: A method for etching a layer over a substrate in a process chamber, wherein the process chamber including a first electrode and a second electrode and the first electrode is disposed opposite of the second electrode is provided. The method includes placing the substrate on the second electrode and providing an etching gas into the process chamber. The method also includes providing a first radio frequency (RF) signal into the process chamber and modulating the first RF signal. The method further includes providing a second RF signal into the process chamber and modulating the second RF signal.

Abstract: There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate.

Abstract: Disclosed herein is a method for manufacturing a micro-electromechanical structure. The method includes the following steps. A circuitry layer having a release feature is formed on an upper surface of a first substrate. A passive layer is formed on the circuitry layer without covering the release feature. The release feature is removed to expose the first substrate by a wet etching process. A portion of the exposed first substrate is anisotropically etched. A second substrate is disposed above the circuitry layer. A cavity is formed in the lower surface of the first substrate. The cavity is filled with a polymeric material. A portion of the first substrate under the microstructure is removed to release the micro-electromechanical structure.

Abstract: A plasma etching method is provided to perform a plasma etching on a silicon oxide film or a silicon nitride film formed below an amorphous carbon film by using a pattern of the amorphous carbon film as a final mask in a multilayer mask including a photoresist layer having a predetermined pattern, an organic bottom anti-reflection coating (BARC) film formed below the photoresist layer, an SiON film formed below the BARC film, and the amorphous carbon film formed below the SiON film. An initial mask used at the time when the plasma etching of the silicon oxide film or the silicon nitride film is started is under a state in which the SiON film remains on the amorphous carbon film and a ratio of a film thickness of the amorphous carbon film to a film thickness of the residual SiON film is smaller than or equal to about 14.

Abstract: Plasma processing methods of a semiconductor manufacturing apparatus which can minimize the amount of impurities adhered to the surface of a wafer, when a desired process using plasma is performed. According to the plasma processing methods of the semiconductor manufacturing apparatus, after the desired process is completed, the plasma generated over the wafer is diffused, and then the wafer is de-chucked.

Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

Abstract: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon layers at the same layer level, wherein the method includes the steps of: forming a photoresist film on the polysilicon layer; forming a photoresist pattern film having side surfaces with different inclination angles by patterning the photoresist film; forming the one or more polysilicon layers having side surfaces with different inclination angles by etching the polysilicon film using the photoresist pattern film.

Abstract: An etching processing method for etching a substrate formed with a target film and a mask film is performed in a substrate processing apparatus including a first and a second power supply for respectively supplying a higher and a lower high frequency power to a processing space and a mounting table, and a DC power supply for supplying a DC power to an electrode. The method includes a modification step for modifying a shape of a pattern formed on the mask film; and an etching step for etching the target film by using the mask film. The mask film is etched by the plasma in the modification step. Further, in the etching step, the DC power is applied to the electrode and the lower high frequency power is applied to the mounting table in a pulse wave form in which a higher and a lower power level are repeated.

Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.

Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Abstract: Disclosed is a substrate processing method configured to prevent the occurrence of a bowing shape to form a hole of a vertical processing shape on a mask layer, and to secure a remaining layer quantity as the mask layer. The substrate processing method receives a wafer W in which a mask layer and an intermediate layer are stacked on a target layer to be processed in a chamber, generates plasma of processing gas in the chamber, performs an etching process on wafer W using the plasma, thereby forming a pattern shape on the target layer to be processed through the intermediate layer and the mask layer. The etching process etches the mask layer by applying excitation power of 500 W for generating plasma, maintaining processing pressure at 5 mTorr (9.31×10?1 Pa) or less, and maintain temperature of wafer W in the range of ?10° C. to ?20° C.

Abstract: The present invention provides a gallium nitride based compound semiconductor light-emitting device having high light emission efficiency and a method of manufacturing the same. The gallium nitride based compound semiconductor light-emitting device includes: a substrate 11; an n-type semiconductor layer 13, a light-emitting layer 14, and a p-type semiconductor layer 15 that are composed of gallium nitride based compound semiconductors and formed on the substrate 11 in this order; a transparent positive electrode 16 that is formed on the p-type semiconductor layer 15; a positive electrode bonding pad 17 that is formed on the transparent positive electrode 16; a negative electrode bonding pad 18 that is formed on the n-type semiconductor layer 13; and an uneven surface that has random convex portions formed thereon and is provided on at least a portion of the surface 16a of the transparent positive electrode 16.

Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

Abstract: A method for selectively etching a nitride layer with respect to a silicon oxide based layer over a substrate is provided. The substrate is placed in a plasma processing chamber. The nitride layer is etched, comprising the steps of flowing a nitride etch gas comprising a hydrocarbon species, an oxygen containing species and a fluorocarbon or hydrofluorocarbon species into the plasma chamber, forming a plasma from the nitride etch gas, and using the plasma from the nitride etch gas to selectively etch the nitride layer with respect to the silicon oxide based layer.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes: arranging a semiconductor substrate on a first electrode out of first and second electrodes arranged to be opposed to each other in a vacuum container; applying negative first pulse voltage and radio-frequency voltage to the first electrode, the negative first pulse voltage being superimposed with the radio-frequency voltage; applying negative second pulse voltage to the second electrode in an off period of the first pulse voltage; and processing the semiconductor substrate or a member on the semiconductor substrate by plasma formed between the first and second electrodes.