Using Abrasion, E.g., Sand-blasting (epo) Patents (Class 257/E21.239)
  • Patent number: 10669185
    Abstract: A method is provided for aligning scoring tools and for scoring glass, in particular thin glass, along predetermined scoring lines in preparation for breaking along the score. Glass substrates, in particular thin glass substrates, produced by such method are also provided. The method includes the determination of the actual orientation of the cutting edge of the scoring tool and aligning of the cutting edge to a target orientation of the cutting edge.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: June 2, 2020
    Assignee: SCHOTT AG
    Inventors: Matthias Jotz, Volker Plapper, Juergen Vogt
  • Patent number: 10312143
    Abstract: A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface. The metal member is provided in the through-hole, and includes a cavity therein defined by an internal surface. The metal oxide film coats the internal surface.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuo Migita, Koji Ogiso
  • Patent number: 9721809
    Abstract: Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 1, 2017
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Nao Hattori
  • Patent number: 8859396
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 8592948
    Abstract: The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step, the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 ?m and not more than 1 ?m on a line of 10 mm.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: November 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki Matsumoto
  • Patent number: 8420503
    Abstract: A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: April 16, 2013
    Assignee: Shin—Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Makoto Kawai, Atsuo Ito, Yoshihiro Kubota, Kouichi Tanaka, Yuji Tobisaka, Hiroshi Tamura
  • Publication number: 20130045598
    Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Jerry Lee, Raymond L. Lavoie, JR., Guangyun Zhang
  • Publication number: 20120322265
    Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Wei HSU, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Chang-Hung Kung, Chia-His Chen, Yen-Ming Chen
  • Publication number: 20120289060
    Abstract: In a wafer processing method, the back side of a wafer having a plurality of devices on the front side thereof is ground, thereby reducing the thickness of the wafer to a predetermined thickness. The back side of the wafer is polished after performing the back grinding step, thereby removing a grinding strain, and a silicon nitride film is formed on the back side of the wafer. The thickness of the silicon nitride film to be formed in the silicon nitride film forming step is set to 6 to 100 nm. Thus, the silicon nitride film having a thickness of 6 to 100 nm is formed on the polished back side of the wafer from which a grinding strain has been removed. Accordingly, each device constituting the wafer can ensure a sufficient die strength and a sufficient gettering effect.
    Type: Application
    Filed: April 19, 2012
    Publication date: November 15, 2012
    Applicant: DISCO CORPORATION
    Inventors: Seiji Harada, Yoshikazu Kobayashi
  • Patent number: 8288251
    Abstract: Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method comprising the steps of: etching 10 nm or more of a surface of a silicon film of an SOI substrate; sandblasting a backside of the SOI substrate with protective tape attached to the etched surface of the silicon film, the back side being the other side of the SOI substrate from the etched surface; removing the protective tape after the sandblasting; and polishing and cleaning a silicon film surface from which the protective tape has been removed.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 16, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Publication number: 20120258564
    Abstract: The present disclosure provides one embodiment of a method. The method includes providing a semiconductor substrate having a front side and a backside, wherein the front side of the semiconductor substrate includes a plurality of backside illuminated imaging sensors; bonding a carrier substrate to the semiconductor substrate from the front side; thinning the semiconductor substrate from the backside; performing an ion implantation to the semiconductor substrate from the backside; performing a laser annealing process to the semiconductor substrate from the backside; and thereafter, performing a polishing process to the semiconductor substrate from the backside.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung Chien Wang, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 8268643
    Abstract: The present invention provides a substrate formed at a low cost and having a controlled plate shape, an epitaxial layer provided substrate obtained by forming an epitaxial layer on the substrate, and methods for producing them. The method for producing the substrate according to the present invention includes an ingot growing step serving as a step of preparing an ingot formed of gallium nitride (GaN); and a slicing step serving as a step of obtaining a substrate formed of gallium nitride, by slicing the ingot. In the slicing step, the substrate thus obtained by the slicing has a main surface with an arithmetic mean roughness Ra of not less than 0.05 ?m and not more than 1 ?m on a line of 10 mm.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 18, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki Matsumoto
  • Publication number: 20120196442
    Abstract: A chemical mechanical polishing method includes providing a semiconductor substrate having a dielectric layer formed thereon, wherein the dielectric layer includes vias and/or grooves, forming a stop layer on the dielectric layer and on sidewalls and bottoms of the vias and/or grooves; forming a metal layer on the stop layer, which completely fills the vias and/or grooves. The method further includes grinding the metal layer until the stop layer is exposed, removing a portion of the stop layer with a first grinding slurry, and removing the stop layer left over with a second grinding slurry until the dielectric layer is exposed, wherein a quantity and a diameter of oxide grinding particles in the second grinding slurry are smaller than those in the first grinding slurry. The method guarantees a removal rate that is equal to conventional art and prevents damage to the wafer so that the products thus made have an improved quality and performance.
    Type: Application
    Filed: September 23, 2011
    Publication date: August 2, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: WUFENG DENG
  • Publication number: 20120164833
    Abstract: Afforded are a polishing agent, and a compound semiconductor manufacturing method and semiconductor device manufacturing method utilizing the agent, whereby the surface quality of compound semiconductor substrates can be favorably maintained, and high polishing rates can be sustained as well. The polishing agent is a polishing agent for Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductors, and includes an alkali metal carbonate, an alkali metal organic salt, a chlorine-based oxidizer, and an alkali metal phosphate, wherein the sum of the concentrations of the alkali metal carbonate and the alkali metal organic salt is between 0.01 mol/L and 0.02 mol/L, inclusive. The compound semiconductor manufacturing method comprises a step of preparing a Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductor, and a step of polishing the face of the compound semiconductor utilizing an aforedescribed polishing agent.
    Type: Application
    Filed: March 9, 2012
    Publication date: June 28, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Masashi Futamura, Takayuki Nishiura
  • Patent number: 8183669
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 22, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Publication number: 20120100718
    Abstract: The CMP polishing liquid for polishing palladium of this invention comprises an organic solvent, 1,2,4-triazole, a phosphorus acid compound, an oxidizing agent and an abrasive. The substrate polishing method is a method for polishing a substrate with a polishing cloth while supplying a CMP polishing liquid between the substrate and the polishing cloth, wherein the substrate is a substrate with a palladium layer on the side facing the polishing cloth, and the CMP polishing liquid is a CMP polishing liquid comprising an organic solvent, 1,2,4-triazole, a phosphorus acid compound, an oxidizing agent and an abrasive.
    Type: Application
    Filed: February 5, 2010
    Publication date: April 26, 2012
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Hisataka Minami, Ryouta Saisyo, Jin Amanokura, Yuuhei Okada, Hiroshi Ono
  • Publication number: 20120064721
    Abstract: The present invention relates to polishing slurry and polishing method used for polishing in a process for forming wirings of a semiconductor device, and the like. There are provided polishing slurry giving a polished surface having high flatness even if the polished surface is made of two or more substances, and further, capable of suppressing metal residue and scratches after polishing, and a method of chemical mechanical polishing using this. The polishing slurry of the present invention is polishing slurry containing at least one of a surfactant and an organic solvent, and a metal oxide dissolving agent and water, or polishing slurry containing water and abrasive of which surface has been modified with an alkyl group, and preferably, it further contains a metal oxidizer, water-soluble polymer, and metal inhibitor.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Applicant: HITACHI CHEMICAL CO., LTD.
    Inventors: Jin Amanokura, Takafumi Sakurada, Sou Anzai, Masato Fukasawa, Shouichi Sasaki
  • Patent number: 8039314
    Abstract: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Danielle L. DeGraw, Peter James Lindgren, Da-Yuan Shih, Ping-Chuan Wang
  • Publication number: 20110237078
    Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 29, 2011
    Applicant: HITACHI METALS, LTD.
    Inventor: Taisuke HIROOKA
  • Patent number: 7977234
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7919343
    Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: April 5, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Naoki Matsumoto, Masato Irikura
  • Patent number: 7872331
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Publication number: 20100279488
    Abstract: Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method comprising the steps of: etching 10 nm or more of a surface of a silicon film of an SOI substrate; sandblasting a backside of the SOI substrate with protective tape attached to the etched surface of the silicon film, the back side being the other side of the SOI substrate from the etched surface; removing the protective tape after the sandblasting; and polishing and cleaning a silicon film surface from which the protective tape has been removed.
    Type: Application
    Filed: April 26, 2010
    Publication date: November 4, 2010
    Inventor: Shoji Akiyama
  • Publication number: 20100159699
    Abstract: To provide selective exposure of the TSV tip through a semiconductor wafer without undercut, the inventor has developed a new method of semiconductor device formation. An embodiment of the present teachings can include the use of sandblasting to remove a portion of the semiconductor wafer to expose the TSV tip without the need for additional wet and/or dry etching.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 24, 2010
    Inventor: Yoshimi Takahashi
  • Patent number: 7718526
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7666689
    Abstract: A method holds wafers that contain patterned structures using a particle blasting tool. Next, the method directs particles at the patterned structures, such that the particles contact the patterned structures with a predetermined velocity and remove the patterned structures. This process of directing the particles at the wafer is controlled to stop directing the particles when substantially all of the patterned structures are removed from the wafer. This process also comprises selecting the particles to have a size equal to or less than 3 microns. For example, the particles can comprise aluminum oxide, silicon oxide, cerium, and/or a plastic. By maintaining the particle size equal to 3 microns or less, the blasting produces a substantially smooth wafer surface, thereby omitting the need for subsequent wafer polishing. Further, the wafers produced by such processing do not exhibit the highly stress lattice and fragile nature of wafers processed by wet processing.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, David Domina, James L. Hardy, Timothy Krywanczyk
  • Patent number: 7662239
    Abstract: Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f), backward (b) or inward (u) with thermoplastic wax having a thickness of 10 ?m or less, grinding the as-grown wafers, lapping the ground wafers, polishing the lapped wafers into mirror wafers with a bevel of a horizontal width of 200 ?m or less and a vertical depth of 100 ?m or less.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: February 16, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Masato Irikura, Seiji Nakahata
  • Publication number: 20090270017
    Abstract: A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 29, 2009
    Applicant: International Business Machines Corporation
    Inventors: Graham M. Bates, David Domina, James L. Hardy, JR., Eric J. White
  • Publication number: 20090256241
    Abstract: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer; a mirror surface forming step S4 of processing the rear surface of the silicon wafer into a mirror surface using a chemical mechanical polishing method; and a modifying step S5 of dispersing abrasive grains that are harder than those used to form the mirror surface in the mirror surface forming process and forming a damaged layer, serving as a gettering sink for heavy metal, on the rear surface of the silicon wafer using the chemical mechanical polishing method. The thickness T5b of the damaged layer W5b in a wafer depth direction is set by the chemical mechanical polishing method in the modifying step S5 to control the gettering capability of the damaged layer.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 15, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Kazunari KURITA, Shuichi OMOTE
  • Publication number: 20090203297
    Abstract: The invention relates to a process for producing a semiconductor wafer by double-side grinding of the semiconductor wafer, in which the semiconductor wafer is simultaneously ground on both sides, first by rough-grinding and then by finish-grinding, using a grinding tool. The semiconductor wafer, between the rough-grinding and the finish-grinding, remains positioned in the grinding machine, and the grinding tool continues to apply a substantially constant load during the transition from rough-grinding to finish-grinding. The invention also relates to an apparatus for carrying out the process and to a semiconductor wafer having a local flatness value on a front surface of less than 16 nm in a measurement window of 2 mm×2 mm area and of less than 40 nm in a measurement window of 10 mm×10 mm area.
    Type: Application
    Filed: November 16, 2007
    Publication date: August 13, 2009
    Applicant: SILTRONIC AG
    Inventors: Georg Pietsch, Michael Kerstan, Werner Blaha
  • Publication number: 20090136724
    Abstract: Embodiments relate to a semiconductor device and to a method of fabricating a semiconductor device. According to embodiments, reliability may be enhanced by removing oxide from a barrier metal surface. According to embodiments, a method may include forming an insulating layer on and/or over a metal layer formed on and/or over a substrate, forming a via hole by etching the insulating layer to expose the metal layer, forming a trench by etching a portion of the insulating layer in an area having the via hole formed therein, forming a barrier metal layer on and/or over the insulating layer including the trench and the via hole, performing plasma processing on the barrier metal layer, and forming a seed Cu layer on the barrier metal layer.
    Type: Application
    Filed: October 17, 2008
    Publication date: May 28, 2009
    Inventor: Sang-Chul Kim
  • Publication number: 20090130849
    Abstract: A composition and associated method for chemical mechanical planarization (or other polishing) is described. The composition contains an amidoxime compound and water. The composition may also contain an abrasive and a compound with oxidation and reduction potential. The composition is useful for attaining improved removal rates for metal, including copper, barrier material, and dielectric layer materials in metal CMP. The composition is particularly useful in conjunction with the associated method for metal CMP applications.
    Type: Application
    Filed: October 29, 2008
    Publication date: May 21, 2009
    Inventor: Wai Mun Lee
  • Publication number: 20090104778
    Abstract: Disclosed is a polishing composition for CMP which contains a polyglycerol derivative (A) represented by following Formula (1): RO—(C3H6O2)n—H ??(1) wherein R represents one selected from a hydroxyl-substituted or unsubstituted alkyl group having one to eighteen carbon atoms, a hydroxyl-substituted or unsubstituted alkenyl or alkapolyenyl group having two to eighteen carbon atoms, an acyl group having two to twenty-four carbon atoms, and hydrogen atom; and “n” denotes an average degree of polymerization of glycerol units and is an integer of 2 to 40; an abrasive (B); and water.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 23, 2009
    Inventors: Yuichi Sakanishi, Hidetoshi Omori
  • Publication number: 20090087988
    Abstract: A polishing liquid is provided which is used for polishing a barrier layer of a semiconductor integrated circuit, the polishing liquid including surface modified particles that include organic polymer particles having at least one inorganic atom selected from the group consisting of Ti, Al, Zr and Si bonded to the organic polymer particles via an oxygen atom present on a surface of the organic polymer particles, an organic acid, an azole compound having at least two carboxyl groups, and an oxidizing agent, the polishing liquid having a pH of from 1 to 7; and a polishing method for polishing a barrier layer of a semiconductor integrated circuit is also provided.
    Type: Application
    Filed: September 22, 2008
    Publication date: April 2, 2009
    Applicant: FUJIFILM Corporation
    Inventor: Toshiyuki Saie
  • Publication number: 20090081871
    Abstract: The inventive method comprises chemically-mechanically polishing a substrate with an inventive polishing composition comprising a liquid carrier, a cationic polymer, an acid, and abrasive particles that have been treated with an aminosilane compound.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 26, 2009
    Applicant: Cabot Microelectronics Corporation
    Inventors: Jeffrey Dysard, Sriram Anjur, Steven Grumbine, Daniela White, William Ward
  • Publication number: 20090075479
    Abstract: A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the copper wiring. A plasma treatment is carried out on a surface of copper exposed at a bottom of the opening without turning plasma discharge of f after forming the opening in the same chamber as the formation of the opening.
    Type: Application
    Filed: November 6, 2008
    Publication date: March 19, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Kenji Tabaru
  • Publication number: 20090068841
    Abstract: There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 ?m, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 ?m, and a surfactant having a hydrophilic moiety.
    Type: Application
    Filed: October 24, 2008
    Publication date: March 12, 2009
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano, Atsushi Shigeta
  • Publication number: 20090061630
    Abstract: A method using an associated composition for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) is described. This method affords low dishing and local erosion levels on the metal during CMP processing of the metal-containing substrate.
    Type: Application
    Filed: August 21, 2008
    Publication date: March 5, 2009
    Applicant: DuPont Air Products Nanomaterials LLC
    Inventors: Bentley J. Palmer, Ann Marie Meyers, Suresh Shrauti, Guangying Zhang, Ajoy Zutshi
  • Publication number: 20090053896
    Abstract: A water-soluble polymer is effective as a removal rate enhancer in a chemical mechanical polishing slurry to polish copper on semiconductor wafers or other copper laid structures, while keeping the etching rate low. The slurry may also include soft particles and certain metal chelating agents, or combinations thereof. The slurry can also comprise an abrasive particle, an organic acid, and an oxidizer.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 26, 2009
    Inventors: Bin Hu, Richard Wen, Deepak Mahulikar
  • Publication number: 20090047786
    Abstract: The present invention provides a CMP abrasive slurry for polishing insulation film, that allow efficiently and high-speed polishing of insulation films such as SiO2 film and SiOC film in the CMP method of flattening an interlayer insulation film, a BPSG film, an insulation film for shallow trench isolation, or a wiring-insulating film layer, a polishing method by using the abrasive slurry, and a semiconductor electronic part polished by the polishing method. A CMP abrasive slurry for polishing insulation film containing cerium oxide particles, a dispersant, a water-soluble polymer having amino groups on the side chains and water, a polishing method by using the CMP abrasive slurry, and a semiconductor electronic part polished by the polishing method.
    Type: Application
    Filed: January 31, 2007
    Publication date: February 19, 2009
    Inventors: Masato Fukasawa, Kazuhiro Enomoto, Chiaki Yamagishi, Naoyuki Koyama
  • Patent number: 7485492
    Abstract: A process for manufacturing a non-volatile memory structure, in particular of a cross-point type provided with an array of memory cells, including forming bottom electrodes on a substrate; forming areas of active material on the bottom electrodes; and forming top electrodes on the areas of active material. The memory cells are defined at the intersection of the bottom electrode with the top electrode. At least one from among the steps of forming bottom electrodes, forming areas of active material, and forming top electrodes includes using soft-lithography techniques, chosen from amongst “microtransfer molding”, “micromolding in capillary”, and “microcontact printing”.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: February 3, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Raffaele Vecchione, Roberta Cuozzo, Anna Morra, Teresa Napolitano
  • Publication number: 20080280442
    Abstract: A method for fabricating a semiconductor device is provided. A substrate includes two different regions, each of which has a different pattern density. A polish target layer is formed over the substrate to cover the patterns in the regions and a planarization guide layer is formed along a top surface of the polish target layer. The planarization guide layer has a polish selectivity ratio with respect to the polish target layer. Subsequently, the planarization guide layer formed in a first region is removed such that the planarization guide layer remains only in a second region having the patterns with low pattern density and the remaining planarization guide layer and the polish target layer are polished to remove a step between the first and second regions.
    Type: Application
    Filed: December 20, 2007
    Publication date: November 13, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Hyon Kwak, Kyoung-Sik Han
  • Publication number: 20080254628
    Abstract: A chemical mechanical polishing process including a single copper removal CMP slurry formulation for planarization of a microelectronic device structure preferably having copper deposited thereon. The process includes the bulk removal of a copper layer using a first CMP slurry formulation having oxidizing agent, passivating agent, abrasive and solvent, and the soft polishing and over-polishing of the microelectronic device structure using a formulation including the first CMP slurry formulation and at least one additional additive. The CMP process described herein provides a high copper removal rate, a comparatively low barrier material removal rate, appropriate material selectivity ranges to minimize copper dishing at the onset of barrier material exposure, and good planarization efficiency.
    Type: Application
    Filed: February 5, 2008
    Publication date: October 16, 2008
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Karl E. Boggs, Michael S. Darsillo, Peter Wrschka, James Welch
  • Publication number: 20080227298
    Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 18, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Toshiyuki HIROTA
  • Publication number: 20080194071
    Abstract: A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 14, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Tsan Yeh, Chih-Hsien Lo, Chin-Ta Su, Kuang-Chao Chen
  • Publication number: 20080188079
    Abstract: The present invention provides a metal-polishing composition for use in chemical mechanical polishing of semiconductor devices, comprising: (a) a compound represented by the following Formula A, (b) a compound represented by the following Formula B, (c) an abrasive grain, and (d) an oxidizing agent: in Formula A, R1 represents an alkyl group having 1 to 3 carbon atoms; and R2 represents a hydrogen atom or an alkyl group having 1 to 4 carbon atoms, and in Formula B, R3, R4, and R5 each independently represent a hydrogen atom, or an alkyl, aryl, alkoxy, amino, aminoalkyl, hydroxy, hydroxyalkyl, carboxy, carboxyalkyl or carbamoyl group.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 7, 2008
    Applicant: FUJIFILM CORPORATION
    Inventors: Tomoo KATO, Takamitsu Tomiga, Makoto Kikuchi, Sumi Takamiya
  • Publication number: 20080119051
    Abstract: A method of removing polysilicon in preference to silicon dioxide and/or silicon nitride by chemical mechanical polishing. The method removes polysilicon from a surface at a high removal rate while maintaining a high selectivity of polysilicon to silicon dioxide and/or a polysilicon to silicon nitride. The method is particularly suitable for use in the fabrication of MEMS devices.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 22, 2008
    Applicants: Clarkson University, Infotonics Technology Center Inc.
    Inventors: Suryadevara V. Babu, Anita Natarajan, Sharath Hegde
  • Patent number: 7371685
    Abstract: Apparatus and methods of fabricating an interconnect in a dielectric material, such as by a damascene or dual damascene processes. In specific, with the use of a barrier layer, such as to contain copper-containing materials used in the fabrication of the interconnect, a slurry jet is used to remove the barrier layer without significantly damaging underlying dielectric material. Such a process is particularly useful when low-k dielectrics are used as the dielectric material, as low-k dielectrics can be easily damaged by known barrier layer removal techniques.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventor: Paul Fischer
  • Publication number: 20080036040
    Abstract: A semiconductor wafer has a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side of the edge having a defined edge profile, the edge profile being substantially constant over the entire circumference of the semiconductor wafer. A method for producing such a wafer allows for production of a multiplicity of semiconductor wafers, the edge profile being substantially constant from semiconductor wafer to semiconductor wafer.
    Type: Application
    Filed: July 26, 2007
    Publication date: February 14, 2008
    Applicant: SILTRONIC AG
    Inventors: Peter Wagner, Hans Adolf Gerber, Anton Huber, Joerg Moser