Mechanical Treatment, E.g., Grinding, Polishing, Cutting (epo) Patents (Class 257/E21.237)
  • Patent number: 10818523
    Abstract: A dividing apparatus divides a workpiece along projected dicing lines into chips, the workpiece being stuck to an upper surface of a protective tape mounted on an annular frame. The dividing apparatus includes a frame holding unit for holding the annular frame and a dividing unit for pressing the workpiece in the vicinity of one at a time of the projected dicing lines and dividing the workpiece into chips along the projected dicing line. The dividing unit includes a holder for holding a portion of the workpiece in the vicinity of the projected dicing line where the workpiece is to be broken, from both upper and lower surfaces of the workpiece, and a presser for pressing chips next to chips held by the holder across the projected dicing line where the workpiece is to be broken, thereby to divide the workpiece along the projected dicing line.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 27, 2020
    Assignee: DISCO CORPORATION
    Inventors: Chris Mihai, Kazuki Kaneoka, Takushi Takahara, Makoto Hirate
  • Patent number: 10788693
    Abstract: A flexible display device is disclosed. The flexible display device may include a flexible substrate, a display device layer on a first surface of the flexible substrate, a receiving groove in a second surface of the flexible substrate, and a deformation-preventing layer in the receiving groove on the second surface of the flexible substrate.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 29, 2020
    Assignee: LG Display Co., Ltd
    Inventors: Hoiyong Kwon, MiReum Lee
  • Patent number: 10770350
    Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10685863
    Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10610973
    Abstract: A wafer producing method for producing a hexagonal single crystal wafer from a hexagonal single crystal ingot, including a separation start point forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the ingot's upper surface, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam while relatively moving the focal point and the ingot to thereby form: (i) a modified layer parallel to the ingot's upper surface, and (ii) cracks extending from the modified layer, thus forming a separation start point. The laser beam is applied to form the modified layer in a condition where the relation of ?0.3?(d?x)/d?0.5 holds, where d is the diameter of a focused spot of the laser beam and x is the spacing between adjacent focused spots of the laser beam.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 7, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kazuya Hirata
  • Patent number: 10553491
    Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: February 4, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10468400
    Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Kyu Kang, Seok Ho Kim, Tae Yeong Kim, Kwang Jin Moon, Ho Jin Lee
  • Patent number: 10395967
    Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
  • Patent number: 10388548
    Abstract: A method of certifying uniform distribution of mechanical pressure comprises an apparatus for moving an object, the apparatus including an arm (410) with a joint (430) for adjusting a fixture (420) having a flat surface area (420a). The fixture includes vacuum suction for holding the object. The method further uses a pressure sensor (450) with a flat surface area (450a), displaying output voltage as a function of mechanical pressure applied. When the sensor is placed on a chuck with vacuum suction, the apparatus moves (460) to bring the flat fixture surface in touch with the flat sensor. Mechanical pressure is applied from the fixture to the sensor; the voltage output of the sensor is monitored to certify uniform distribution of the fixture pressure across the sensor area.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dori Alon Robissa
  • Patent number: 10373871
    Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Brunnbauer, Franco Mariani
  • Patent number: 10325861
    Abstract: Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventor: Giuseppe Miccoli
  • Patent number: 10269642
    Abstract: Die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10269609
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10211361
    Abstract: A method of manufacturing a solar cell comprising providing a first semiconductor substrate with an epitaxial sequence of layers of semiconductor material forming a solar cell deposited over the first semiconductor substrate using an MOCVD reactor; depositing a metal layer on top of the sequence of layers of semiconductor material, the metal layer including a top surface layer composed of gold or silver; providing a polymer film; depositing a first metallic adhesion layer that has a coefficient of thermal expansion substantially different from that of the top surface layer on one surface of the polymer film; depositing a second metal adhesion layer over the first metallic adhesion layer and having a different composition from the first layer and having no chemical elements in common; and adjoining the second adhesion layer of the polymer film to the metal layer of the sequence of layers and permanently bonding it thereto by a thermocompressive diffusion bonding technique.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 19, 2019
    Assignee: SolAero Technologies Corp.
    Inventors: Michael Riley, Mark Stan, Arthur Cornfeld
  • Patent number: 10211367
    Abstract: An LED fabrication method includes forming release holes by focusing a laser at the substrate back surface, and forming stealth laser-blast areas by focusing a laser inside the substrate on positions corresponding to the release holes; communicating the release holes with the stealth laser-blast areas to release impurities generated during forming of the stealth laser-blast areas from the substrate through the release holes, thereby avoiding low external quantum efficiency resulting from adherence of the released material to the side wall of the stealth laser-blast areas. By focusing on a position with 10 ?m˜40 ?m inward from the substrate back side, adjusting laser energy and frequency to burn holes inside the substrate to penetrate and expose the substrate back surface, thereby effectively removing by-products, and reducing light absorption by such by-products, light extraction from a side wall of the LED can also be improved and light extraction efficiency is enhanced.
    Type: Grant
    Filed: May 27, 2017
    Date of Patent: February 19, 2019
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chia-hung Chang, Gong Chen, Su-hui Lin, Kang-wei Peng, Sheng-hsien Hsu, Chuan-gui Liu, Xiao-xiong Lin, Yu Zhou, Jing-jing Wei, Jing Huang
  • Patent number: 10163848
    Abstract: A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Chih-Chien Pan
  • Patent number: 10134577
    Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard F. Indyk, Deepika Priyadarshini, Spyridon Skordas, Edmund J. Sprogis, Anthony K. Stamper, Kevin R. Winstel
  • Patent number: 10068801
    Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: September 4, 2018
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
  • Patent number: 9978722
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: William T. Glennan, Frank D. Madrigal
  • Patent number: 9859144
    Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Patent number: 9852949
    Abstract: A wafer is divided into device chips each of which is surrounded by a mold resin. The wafer has a plurality of devices arranged like a matrix with a spacing having a predetermined width, the front side of each device being covered with the mold resin, the spacing being filled with the mold resin to form a street between any adjacent ones of the devices. The wafer processing method includes a division start point forming step of forming a division start point along each street at the lateral center of the mold resin filling the spacing and a dividing step of applying an external force to the wafer after performing the division start point forming step, thereby laterally dividing each street into two parts at the division start point to obtain the device chips divided from each other, each device chip being surrounded by the mold resin.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: December 26, 2017
    Assignee: Disco Corporation
    Inventors: Tetsukazu Sugiya, Xin Lu
  • Patent number: 9847445
    Abstract: LED dies are partially singulated while on an unthinned depth growth substrate. Slots are made through the streets separating the LED dies, but not through the growth substrate, leaving the now separated LED dies on the growth substrate. A secondary support is attached to the LED dies on the opposite surface from the growth substrate, and the growth substrate is thinned or removed, leaving the LED dies on the secondary support. Because the LED dies are separated while on the unthinned growth substrate, the likelihood of distortion before slicing is virtually eliminated, and the width of the streets between the LED dies may be correspondingly reduced.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 19, 2017
    Assignee: Koninklijke Philips N.V.
    Inventor: Frank Wei
  • Patent number: 9829806
    Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Patent number: 9786509
    Abstract: A wafer processing method includes a first grinding step and a second grinding step. In the first grinding step, first grinding abrasives are moved in a processing feed direction that is a direction orthogonal to a holding surface of a chuck table of grinding apparatus and a wafer is ground to form a first circular recess in the back surface of the wafer. In the second grinding step, second grinding abrasives formed of finer abrasive grains than the first grinding abrasives are moved down in an oblique direction from the center side of the wafer toward the periphery of the wafer and the first circular recess is ground.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 10, 2017
    Assignee: Disco Corporation
    Inventors: Ryosuke Nishihara, Minoru Matsuzawa, Kohei Tsujimoto, Tetsukazu Sugiya
  • Patent number: 9761474
    Abstract: Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Sony Varghese
  • Patent number: 9754811
    Abstract: [Problem] To provide a dicing sheet that is with a protective film formation layer, can easily produce a semiconductor chip having a protective film having high uniformity and superior printing precision, is such that the peeling of the protective film and the dicing sheet can be easily performed, and has superior affixing ability of chips during dicing. [Solution] The dicing sheet with a protective film formation layer is characterized by a protective film formation layer being peelably provided on the adhesive layer of an adhesive sheet resulting from the adhesive layer, which contains an adhesive component and a free epoxy group-containing compound, being laminated onto a substrate film.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 5, 2017
    Assignee: LINTEC CORPORATION
    Inventors: Naoya Saeki, Tomonori Shinoda, Ken Takano
  • Patent number: 9711405
    Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 18, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
  • Patent number: 9682440
    Abstract: A chip having a desired shape is formed from a platelike workpiece. The chip manufacturing method includes a shield tunnel forming step of applying a pulsed laser beam to the workpiece from a focusing unit included in a pulsed laser beam applying unit along the contour of the chip to be formed, with the focal point of the pulsed laser beam set at a predetermined depth from the upper surface of the workpiece, thereby forming a plurality of shield tunnels inside the workpiece along the contour of the chip to be formed. Each shield tunnel has a fine hole and an amorphous region formed around the fine hole for shielding the fine hole. In a chip forming step, ultrasonic vibration is applied to the workpiece to break the contour of the chip where the shield tunnels have been formed, thereby forming the chip from the workpiece.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 20, 2017
    Assignee: Disco Corporation
    Inventors: Hiroshi Morikazu, Noboru Takeda
  • Patent number: 9620455
    Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 9564365
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: February 7, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9496337
    Abstract: A method for producing a semiconductor device includes forming a trench that defines a closed loop in a semiconductor body and extends from a first surface into the semiconductor body. The trench has at least one sidewall that is beveled relative to a vertical direction of the semiconductor body. The method further includes removing material of the semiconductor body at least between a bottom of the trench a second surface opposite the first surface of the semiconductor body.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
  • Patent number: 9472458
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines through the semiconductor wafer, and reducing the presence of residual contaminates on the semiconductor wafer.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: October 18, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jason Michael Doub, Gordon M. Grivna
  • Patent number: 9399274
    Abstract: An apparatus and method of polishing a substrate is described. The polishing includes: rotating a substrate; pressing a first polishing tool against an edge portion of the substrate to polish the edge portion; and pressing a second polishing tool against the edge portion of the substrate to polish the edge portion. The second polishing tool is located more inwardly than the first polishing tool with respect to a radial direction of the substrate. The first polishing tool has a polishing surface rougher than a polishing surface of the second polishing tool.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: July 26, 2016
    Assignee: Ebara Corporation
    Inventors: Tetsuji Togawa, Atsushi Yoshida, Toshifumi Watanabe
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 9034733
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 9029239
    Abstract: A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 12, 2015
    Assignee: Sandia Corporation
    Inventors: Anna Tauke-Pedretti, Gregory N. Nielson, Jeffrey G. Cederberg, Jose Luis Cruz-Campa
  • Patent number: 9006010
    Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Arie Shahar, Eliezer Traub, Diego Sclar, Peter Rusian
  • Patent number: 8969175
    Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 3, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Ploessl, Heribert Zull
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8952496
    Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 10, 2015
    Assignee: Sumco Corporation
    Inventor: Sumihisa Masuda
  • Patent number: 8952555
    Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masami Koketsu, Toshiaki Sawada
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8871571
    Abstract: A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: October 28, 2014
    Assignee: UTAC Thai Limited
    Inventor: Saravuth Sirinorakul
  • Patent number: 8865566
    Abstract: Multiphoton absorption is generated, so as to form a part which is intended to be cut 9 due to a molten processed region 13 within a silicon wafer 11, and then an adhesive sheet 20 bonded to the silicon wafer 11 is expanded. This cuts the silicon wafer 11 along the part which is intended to be cut 9 with a high precision into semiconductor chips 25. Here, opposing cut sections 25a, 25a of neighboring semiconductor chips 25, 25 are separated from each other from their close contact state, whereby a die-bonding resin layer 23 is also cut along the part which is intended to be cut 9. Therefore, the silicon wafer 11 and die-bonding resin layer 23 can be cut much more efficiently than in the case where the silicon wafer 11 and die-bonding resin layer 23 are cut with a blade without cutting a base 21.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama, Ryuji Sugiura
  • Patent number: 8841170
    Abstract: A method of singulating semiconductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semiconductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semiconductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 23, 2014
    Assignees: The Regents of the University of California, Naval Research Laboratory
    Inventors: Vitaliy Fadeyev, Hartmut F. W. Sadrozinski, Marc Christophersen, Bernard F. Phlips
  • Patent number: 8828891
    Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Takeshi Sakamoto
  • Patent number: 8802543
    Abstract: A laser processing method which can highly accurately cut objects to be processed having various laminate structures is provided. An object to be processed comprising a substrate and a laminate part disposed on the front face of the substrate is irradiated with laser light L while a light-converging point P is positioned at least within the substrate, so as to form a modified region due to multiphoton absorption at least within the substrate, and cause the modified region to form a starting point region for cutting. When the object is cut along the starting point region for cutting, the object 1 can be cut with a high accuracy.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Patent number: 8791574
    Abstract: In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Minoru Kimura, Masao Odagiri
  • Patent number: 8772177
    Abstract: A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: July 8, 2014
    Assignee: Sumco Corporation
    Inventor: Sumihisa Masuda
  • Patent number: 8753923
    Abstract: A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 17, 2014
    Assignee: Disco Corporation
    Inventors: Satoshi Kobayashi, Jinyan Zhao