Mechanical Treatment, E.g., Grinding, Polishing, Cutting (epo) Patents (Class 257/E21.237)
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Patent number: 12217967Abstract: Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle ? on the main surface side of 0°<??110° for all of the planes A where a distance from the main surface is 100 ?m or more and 200 ?m or less, wherein the angle ? is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature Rf of from 200 to 350 ?m.Type: GrantFiled: December 23, 2020Date of Patent: February 4, 2025Assignee: JX ADVANCED METALS CORPORATIONInventors: Shunsuke Oka, Kenji Suzuki, Hideaki Hayashi
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Patent number: 12068165Abstract: There is provided a method for manufacturing a semiconductor device, including: attracting a semiconductor device wafer by a chuck mechanism and rotating the semiconductor device wafer horizontally; rotating a rotary blade horizontally by a vertical spindle to which ultrasonic waves are applied; trimming an outer peripheral end portion of the semiconductor device wafer that is horizontally rotating by the rotary blade that is horizontally rotating, to form a groove in the outer peripheral end portion; correcting a tip shape of the rotary blade that is horizontally rotating by a blade-forming grinding wheel during the trimming; and grinding one main surface of the semiconductor device wafer that is horizontally rotating by a cup grinding wheel that is horizontally rotating after the trimming.Type: GrantFiled: February 22, 2022Date of Patent: August 20, 2024Assignee: OKAMOTO MACHINE TOOL WORKS, LTD.Inventors: Eiichi Yamamoto, Tsubasa Bando, Takahiko Mitsui
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Patent number: 11969856Abstract: A manufacturing method of a wafer with a notch includes: polishing principal surfaces of the wafer; mirror-polishing a notch chamfered portion of the notch; mirror-polishing an outer-periphery chamfered portion of an outer peripheral portion of the wafer; and finish-polishing one of principal surfaces of the wafer, the finish-polishing being performed after performing the mirror-polishing of the notch chamfered portion, the polishing of the principal surfaces, and the mirror-polishing of the outer-periphery chamfered portion in this order.Type: GrantFiled: November 8, 2019Date of Patent: April 30, 2024Assignee: SUMCO CORPORATIONInventor: Kantarou Torii
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Patent number: 11876015Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.Type: GrantFiled: February 26, 2020Date of Patent: January 16, 2024Assignee: SoitecInventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Franck Colas
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Patent number: 11676844Abstract: A coating film forming apparatus includes a carry-in/out section in which a substrate is carried in and carried out; a periphery coating module configured to form a ring-shaped coating film by supplying a coating liquid along a periphery of the substrate based on a processing parameter for controlling a coating state by the coating film; an imaging module configured to image the substrate on which the ring-shaped coating film is formed; a transfer mechanism configured to transfer the substrate; and a controller configured to output a control signal to perform a process of forming the ring-shaped coating film on the substrate based on the processing parameter having different values and imaging the substrate by the imaging module, and configured to determine, based on an imaging result of the substrate, a value of the processing parameter for forming the ring-shaped coating film on the substrate in the periphery coating module.Type: GrantFiled: June 4, 2019Date of Patent: June 13, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Akiko Kiyotomi, Masatoshi Kawakita
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Patent number: 11574804Abstract: A processing apparatus used in processing a workpiece having a device in each of a plurality of regions that includes a chuck table holding the workpiece, positioning means positioning the workpiece before grinding, resin coating means including a rotatable spinner table for coating the workpiece with a resin, cleaning means, a grinding unit, and a transfer unit. The transfer unit includes a first transfer unit transferring the workpiece from the positioning means to the spinner table and from the spinner table to the chuck table, a second transfer unit transferring the workpiece from the chuck table to the cleaning means, and a front/back surface inversion transfer unit taking over the workpiece from the cleaning means to the second transfer unit.Type: GrantFiled: December 11, 2018Date of Patent: February 7, 2023Assignee: DISCO CORPORATIONInventors: Shinya Watanabe, Ichiro Yamahata, Katsuhiko Suzuki
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Patent number: 11488866Abstract: A method for dividing a package substrate into a plurality of device packages. The package substrate has a mount surface on the front side where a plurality of division lines are formed and a sealing layer formed on the back side, in which devices are sealed. The method includes a groove forming step of forming a groove along each division line on the mount surface of the package substrate so that the groove has a depth corresponding to a finished thickness of each device package, a burr removing step of removing burrs produced from electrodes in the groove forming step, and a grinding step of grinding the sealing layer of the package substrate so that a thickness of the package substrate is reduced to the finished thickness, after performing the burr removing step, thereby dividing the package substrate into the plural device packages.Type: GrantFiled: November 21, 2019Date of Patent: November 1, 2022Assignee: DISCO CORPORATIONInventors: Wai Kit Choong, Eric Chong
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Patent number: 11469180Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.Type: GrantFiled: May 28, 2020Date of Patent: October 11, 2022Inventors: Junyeong Heo, Unbyoung Kang, Donghoon Won
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Patent number: 11393721Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip from the polyester sheet side to push up each device chip through the polyester sheet and picking up each device chip from the polyester sheet.Type: GrantFiled: September 9, 2020Date of Patent: July 19, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11380585Abstract: A semiconductor device manufacturing method includes thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by grinding a central portion of a back surface of the wafer and then performing wet etching on the back surface of the wafer, forming a backside electrode on the back surface of the wafer, performing plating to evenly form a metal film on a portion of the backside electrode on the annular protruding portion, attaching a dicing tape to the metal film, and dicing the wafer having the dicing tape attached thereto.Type: GrantFiled: April 20, 2015Date of Patent: July 5, 2022Assignee: Mitsubishi Electric CorporationInventors: Ryuji Ueno, Masatoshi Sunamoto
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Patent number: 11322406Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet.Type: GrantFiled: June 30, 2020Date of Patent: May 3, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11302578Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyolefin sheet, then picking up each device chip from the polyolefin sheet.Type: GrantFiled: May 8, 2020Date of Patent: April 12, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11289379Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.Type: GrantFiled: July 31, 2020Date of Patent: March 29, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11270916Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyolefin sheet, then picking up each device chip from the polyolefin sheet.Type: GrantFiled: June 30, 2020Date of Patent: March 8, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11251082Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet.Type: GrantFiled: May 8, 2020Date of Patent: February 15, 2022Assignee: DISCO CORPORATIONInventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
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Patent number: 11222823Abstract: A wafer processing method for dividing a wafer into individual device chips. The wafer processing method includes a thermocompression bonding sheet providing step of positioning the wafer in an inside opening of a ring frame and providing a thermocompression bonding sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the thermocompression bonding sheet as applying a pressure to the thermocompression bonding sheet to thereby unite the wafer and the ring frame through the thermocompression bonding sheet by thermocompression bonding, a dividing step of cutting the wafer to thereby form a plurality of dividing grooves and dividing the wafer into the individual device chips, a flattening step of flattening the thermocompression bonding sheet, and a back side observing step of observing the back side of each device chip through the thermocompression bonding sheet.Type: GrantFiled: February 4, 2020Date of Patent: January 11, 2022Assignee: DISCO CORPORATIONInventor: Kazuma Sekiya
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Patent number: 11087970Abstract: A bonded wafer includes: a first wafer having a first surface and a second surface opposite to the first surface, and including a functional element on the first surface; and a second wafer in which a structure having at least one of a hole, a groove and a cavity is formed; wherein an annular protrusion is formed to have a shape to extend along an outer periphery on the second surface of the first wafer; wherein at least a portion of the second wafer is a reduced-diameter portion having a diameter smaller than an inner diameter of the annular protrusion; and wherein, under a state in which the reduced-diameter portion is fitted into a region surrounded by the annular protrusion of the first wafer, the second wafer is bonded to the second surface at least at the region.Type: GrantFiled: August 29, 2019Date of Patent: August 10, 2021Assignee: Canon Kabushiki KaishaInventor: Ryoji Kanri
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Patent number: 10991613Abstract: A substrate holding apparatus is provided, which includes a top ring main body to which an elastic film having a surface that can suck a substrate can be attached, a first line communicating with a first area of the plurality of areas, a second line communicating with a second area different from the first area of the plurality of areas, a pressure adjuster that can pressurize the first area by feeding fluid into the first area through the first line and can generate negative pressure in the second area through the second line, and a determiner that performs determination of whether or not the substrate is sucked to the elastic film based on a volume of the fluid fed into the first area or a measurement value corresponding to pressure in the first area.Type: GrantFiled: August 6, 2019Date of Patent: April 27, 2021Assignee: EBARA CORPORATIONInventors: Osamu Nabeya, Satoru Yamaki, Makoto Fukushima
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Patent number: 10953516Abstract: A grinding apparatus includes: a holding table for holding a workpiece thereon; a grinding unit including a grinding wheel for grinding the workpiece held on the holding table, the grinding wheel including a grinding stone made of abrasive grains and grains of photocatalyst bonded by a vitrified bonding material; a grinding water supply unit configured to supply grinding water to the grinding stone when the workpiece held on the holding table is ground by the grinding unit; and a light applying unit disposed adjacent to the holding table and configured to apply light to a grinding surface of the grinding stone while the workpiece held on the holding table being ground.Type: GrantFiled: June 18, 2018Date of Patent: March 23, 2021Assignee: DISCO CORPORATIONInventor: Kenji Takenouchi
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Patent number: 10946498Abstract: The present invention discloses a method and system for machining a work piece by a machining tool, and a robot system using the same. The method comprises: defining a customized contact point on the machining tool by setting a contact point height of the machining tool; moving the machining tool against the work piece to apply predefined machining feeds. Compared with the existing prior arts, the proposed method and system improves machining efficiency and accuracy. With the method and system according to the present disclosure, high machining efficiency could be achieved as well as collisions could be avoided.Type: GrantFiled: November 10, 2015Date of Patent: March 16, 2021Assignee: ABB Schweiz AGInventors: Lei Mao, Shaojie Cheng, Diamond Daimeng Dong
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Patent number: 10943895Abstract: A method of assembling a plurality of linear arrays from a silicon wafer having a first surface and a second surface opposite the first surface, the first surface having at least a first linear array of sensor/emitter elements and a second linear array of sensor/emitter elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of sensor/emitter elements and the second linear array of sensor/emitter elements.Type: GrantFiled: January 14, 2019Date of Patent: March 9, 2021Assignee: Xerox CorporationInventors: Gary D. Redding, Joseph F. Casey
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Patent number: 10818523Abstract: A dividing apparatus divides a workpiece along projected dicing lines into chips, the workpiece being stuck to an upper surface of a protective tape mounted on an annular frame. The dividing apparatus includes a frame holding unit for holding the annular frame and a dividing unit for pressing the workpiece in the vicinity of one at a time of the projected dicing lines and dividing the workpiece into chips along the projected dicing line. The dividing unit includes a holder for holding a portion of the workpiece in the vicinity of the projected dicing line where the workpiece is to be broken, from both upper and lower surfaces of the workpiece, and a presser for pressing chips next to chips held by the holder across the projected dicing line where the workpiece is to be broken, thereby to divide the workpiece along the projected dicing line.Type: GrantFiled: October 5, 2018Date of Patent: October 27, 2020Assignee: DISCO CORPORATIONInventors: Chris Mihai, Kazuki Kaneoka, Takushi Takahara, Makoto Hirate
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Patent number: 10788693Abstract: A flexible display device is disclosed. The flexible display device may include a flexible substrate, a display device layer on a first surface of the flexible substrate, a receiving groove in a second surface of the flexible substrate, and a deformation-preventing layer in the receiving groove on the second surface of the flexible substrate.Type: GrantFiled: December 30, 2015Date of Patent: September 29, 2020Assignee: LG Display Co., LtdInventors: Hoiyong Kwon, MiReum Lee
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Patent number: 10770350Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.Type: GrantFiled: December 16, 2019Date of Patent: September 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Gordon M. Grivna
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Patent number: 10685863Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.Type: GrantFiled: April 27, 2018Date of Patent: June 16, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Michael J. Seddon
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Patent number: 10610973Abstract: A wafer producing method for producing a hexagonal single crystal wafer from a hexagonal single crystal ingot, including a separation start point forming step of setting the focal point of a laser beam inside the ingot at a predetermined depth from the ingot's upper surface, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam while relatively moving the focal point and the ingot to thereby form: (i) a modified layer parallel to the ingot's upper surface, and (ii) cracks extending from the modified layer, thus forming a separation start point. The laser beam is applied to form the modified layer in a condition where the relation of ?0.3?(d?x)/d?0.5 holds, where d is the diameter of a focused spot of the laser beam and x is the spacing between adjacent focused spots of the laser beam.Type: GrantFiled: May 26, 2016Date of Patent: April 7, 2020Assignee: DISCO CORPORATIONInventor: Kazuya Hirata
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Method of separating a back layer on a singulated semiconductor wafer attached to carrier substrates
Patent number: 10553491Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.Type: GrantFiled: March 13, 2019Date of Patent: February 4, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Gordon M. Grivna -
Patent number: 10468400Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.Type: GrantFiled: January 12, 2018Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil Kyu Kang, Seok Ho Kim, Tae Yeong Kim, Kwang Jin Moon, Ho Jin Lee
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Patent number: 10395967Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: GrantFiled: June 20, 2017Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
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Patent number: 10388548Abstract: A method of certifying uniform distribution of mechanical pressure comprises an apparatus for moving an object, the apparatus including an arm (410) with a joint (430) for adjusting a fixture (420) having a flat surface area (420a). The fixture includes vacuum suction for holding the object. The method further uses a pressure sensor (450) with a flat surface area (450a), displaying output voltage as a function of mechanical pressure applied. When the sensor is placed on a chuck with vacuum suction, the apparatus moves (460) to bring the flat fixture surface in touch with the flat sensor. Mechanical pressure is applied from the fixture to the sensor; the voltage output of the sensor is monitored to certify uniform distribution of the fixture pressure across the sensor area.Type: GrantFiled: May 27, 2016Date of Patent: August 20, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Dori Alon Robissa
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Patent number: 10373871Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.Type: GrantFiled: May 1, 2018Date of Patent: August 6, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Markus Brunnbauer, Franco Mariani
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Patent number: 10325861Abstract: Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.Type: GrantFiled: September 30, 2016Date of Patent: June 18, 2019Assignee: Intel IP CorporationInventor: Giuseppe Miccoli
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Patent number: 10269642Abstract: Die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.Type: GrantFiled: May 11, 2018Date of Patent: April 23, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Gordon M. Grivna
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Patent number: 10269609Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: January 30, 2018Date of Patent: April 23, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10211361Abstract: A method of manufacturing a solar cell comprising providing a first semiconductor substrate with an epitaxial sequence of layers of semiconductor material forming a solar cell deposited over the first semiconductor substrate using an MOCVD reactor; depositing a metal layer on top of the sequence of layers of semiconductor material, the metal layer including a top surface layer composed of gold or silver; providing a polymer film; depositing a first metallic adhesion layer that has a coefficient of thermal expansion substantially different from that of the top surface layer on one surface of the polymer film; depositing a second metal adhesion layer over the first metallic adhesion layer and having a different composition from the first layer and having no chemical elements in common; and adjoining the second adhesion layer of the polymer film to the metal layer of the sequence of layers and permanently bonding it thereto by a thermocompressive diffusion bonding technique.Type: GrantFiled: July 27, 2016Date of Patent: February 19, 2019Assignee: SolAero Technologies Corp.Inventors: Michael Riley, Mark Stan, Arthur Cornfeld
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Patent number: 10211367Abstract: An LED fabrication method includes forming release holes by focusing a laser at the substrate back surface, and forming stealth laser-blast areas by focusing a laser inside the substrate on positions corresponding to the release holes; communicating the release holes with the stealth laser-blast areas to release impurities generated during forming of the stealth laser-blast areas from the substrate through the release holes, thereby avoiding low external quantum efficiency resulting from adherence of the released material to the side wall of the stealth laser-blast areas. By focusing on a position with 10 ?m˜40 ?m inward from the substrate back side, adjusting laser energy and frequency to burn holes inside the substrate to penetrate and expose the substrate back surface, thereby effectively removing by-products, and reducing light absorption by such by-products, light extraction from a side wall of the LED can also be improved and light extraction efficiency is enhanced.Type: GrantFiled: May 27, 2017Date of Patent: February 19, 2019Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chia-hung Chang, Gong Chen, Su-hui Lin, Kang-wei Peng, Sheng-hsien Hsu, Chuan-gui Liu, Xiao-xiong Lin, Yu Zhou, Jing-jing Wei, Jing Huang
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Patent number: 10163848Abstract: A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.Type: GrantFiled: April 28, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Chih-Chien Pan
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Patent number: 10134577Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.Type: GrantFiled: May 21, 2015Date of Patent: November 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Richard F. Indyk, Deepika Priyadarshini, Spyridon Skordas, Edmund J. Sprogis, Anthony K. Stamper, Kevin R. Winstel
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Patent number: 10068801Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.Type: GrantFiled: June 8, 2017Date of Patent: September 4, 2018Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
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Patent number: 9978722Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed.Type: GrantFiled: September 29, 2016Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: William T. Glennan, Frank D. Madrigal
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Patent number: 9859144Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.Type: GrantFiled: September 7, 2016Date of Patent: January 2, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
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Patent number: 9852949Abstract: A wafer is divided into device chips each of which is surrounded by a mold resin. The wafer has a plurality of devices arranged like a matrix with a spacing having a predetermined width, the front side of each device being covered with the mold resin, the spacing being filled with the mold resin to form a street between any adjacent ones of the devices. The wafer processing method includes a division start point forming step of forming a division start point along each street at the lateral center of the mold resin filling the spacing and a dividing step of applying an external force to the wafer after performing the division start point forming step, thereby laterally dividing each street into two parts at the division start point to obtain the device chips divided from each other, each device chip being surrounded by the mold resin.Type: GrantFiled: September 1, 2016Date of Patent: December 26, 2017Assignee: Disco CorporationInventors: Tetsukazu Sugiya, Xin Lu
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Patent number: 9847445Abstract: LED dies are partially singulated while on an unthinned depth growth substrate. Slots are made through the streets separating the LED dies, but not through the growth substrate, leaving the now separated LED dies on the growth substrate. A secondary support is attached to the LED dies on the opposite surface from the growth substrate, and the growth substrate is thinned or removed, leaving the LED dies on the secondary support. Because the LED dies are separated while on the unthinned growth substrate, the likelihood of distortion before slicing is virtually eliminated, and the width of the streets between the LED dies may be correspondingly reduced.Type: GrantFiled: March 29, 2013Date of Patent: December 19, 2017Assignee: Koninklijke Philips N.V.Inventor: Frank Wei
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Patent number: 9829806Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.Type: GrantFiled: March 14, 2014Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
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Patent number: 9786509Abstract: A wafer processing method includes a first grinding step and a second grinding step. In the first grinding step, first grinding abrasives are moved in a processing feed direction that is a direction orthogonal to a holding surface of a chuck table of grinding apparatus and a wafer is ground to form a first circular recess in the back surface of the wafer. In the second grinding step, second grinding abrasives formed of finer abrasive grains than the first grinding abrasives are moved down in an oblique direction from the center side of the wafer toward the periphery of the wafer and the first circular recess is ground.Type: GrantFiled: August 25, 2015Date of Patent: October 10, 2017Assignee: Disco CorporationInventors: Ryosuke Nishihara, Minoru Matsuzawa, Kohei Tsujimoto, Tetsukazu Sugiya
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Patent number: 9761474Abstract: Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° C. to separate the another substrate from the carrier substrate. Some methods include forming a polymeric material over a first substrate, securing a second substrate to the first substrate over the polymeric material, cooling the polymeric material to a temperature below a glass transition temperature of the polymeric material, and separating the second substrate from the first substrate. Semiconductor structures may include a polymeric material over at least a portion of a first substrate, an adhesive material over the polymeric material, and a second substrate over the adhesive material. The polymeric material may have a glass transition temperature of about 10° C. or lower and a melting point of about 100° C. or greater.Type: GrantFiled: December 19, 2013Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventor: Sony Varghese
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Patent number: 9754811Abstract: [Problem] To provide a dicing sheet that is with a protective film formation layer, can easily produce a semiconductor chip having a protective film having high uniformity and superior printing precision, is such that the peeling of the protective film and the dicing sheet can be easily performed, and has superior affixing ability of chips during dicing. [Solution] The dicing sheet with a protective film formation layer is characterized by a protective film formation layer being peelably provided on the adhesive layer of an adhesive sheet resulting from the adhesive layer, which contains an adhesive component and a free epoxy group-containing compound, being laminated onto a substrate film.Type: GrantFiled: August 22, 2013Date of Patent: September 5, 2017Assignee: LINTEC CORPORATIONInventors: Naoya Saeki, Tomonori Shinoda, Ken Takano
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Patent number: 9711405Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.Type: GrantFiled: December 30, 2015Date of Patent: July 18, 2017Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
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Patent number: 9682440Abstract: A chip having a desired shape is formed from a platelike workpiece. The chip manufacturing method includes a shield tunnel forming step of applying a pulsed laser beam to the workpiece from a focusing unit included in a pulsed laser beam applying unit along the contour of the chip to be formed, with the focal point of the pulsed laser beam set at a predetermined depth from the upper surface of the workpiece, thereby forming a plurality of shield tunnels inside the workpiece along the contour of the chip to be formed. Each shield tunnel has a fine hole and an amorphous region formed around the fine hole for shielding the fine hole. In a chip forming step, ultrasonic vibration is applied to the workpiece to break the contour of the chip where the shield tunnels have been formed, thereby forming the chip from the workpiece.Type: GrantFiled: May 29, 2015Date of Patent: June 20, 2017Assignee: Disco CorporationInventors: Hiroshi Morikazu, Noboru Takeda
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Patent number: 9620455Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.Type: GrantFiled: June 24, 2010Date of Patent: April 11, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo