Deposition Of Superconductive Layer (epo) Patents (Class 257/E21.298)
  • Patent number: 8237264
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: August 7, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 7897414
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: March 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 7371586
    Abstract: A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a superconducting film in each film deposition is 0.3 ?m or less. In such a case, even when the layer thickness of the superconducting layer is increased, the decrease in the Jc is suppressed and the Ic is increased.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: May 13, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shuji Hahakura, Kazuya Ohmatsu
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7148128
    Abstract: We describe a system of electronically active inks which may include electronically addressable contrast media, conductors, insulators, resistors, semiconductive materials, magnetic materials, spin materials, piezoelectric materials, optoelectronic, thermoelectric or radio frequency materials. We further describe a printing system capable of laying down said materials in a definite pattern. Such a system may be used for instance to: print a flat panel display complete with onboard drive logic; print a working logic circuit onto any of a large class of substrates; print an electrostatic or piezoelectric motor with onboard logic and feedback or print a working radio transmitter or receiver.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: December 12, 2006
    Assignee: E Ink Corporation
    Inventor: Joseph M. Jacobson
  • Patent number: 6777808
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber