Deposition/post-treatment Of Noninsulating, E.g., Conductive - Or Resistive - Layers On Insulating Layers (epo) Patents (Class 257/E21.294)
  • Patent number: 9620610
    Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., LTD.
    Inventors: Shiu-Ko Jangjian, Chi-Cheng Hung, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 9472646
    Abstract: A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Tae-Kyung Oh
  • Patent number: 9240453
    Abstract: A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventor: Tae-Kyung Oh
  • Patent number: 9012320
    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Kil-Su Jeong, Hansoo Kim, Youngwoo Park
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8940626
    Abstract: A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Pranatharthi Haran Balasubramanian
  • Patent number: 8921217
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Patent number: 8866123
    Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
  • Patent number: 8846516
    Abstract: Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nirmal Ramaswamy
  • Patent number: 8809139
    Abstract: Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
  • Patent number: 8779576
    Abstract: In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wook Park, Nam-seog Kim, Seung-duk Baek
  • Patent number: 8772866
    Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 8, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Pyo Hong
  • Patent number: 8766446
    Abstract: A semiconductor memory device comprising a stacked unit, a semiconductor pillar, a charge storage layer, and a non-insulating film. The stacked unit includes first conductive layers and first insulating layers which are stacked alternately. The semiconductor pillar passes through the stacked body and the semiconductor pillar has a tubular structure. The charge storage layer is provided between the semiconductor pillar and each of the first conductive layers. The non-insulating film is provided inside the tubular structure and has a non-insulating member. The first effective impurity concentration of the non-insulating film is lower than a second effective impurity concentration of the semiconductor pillar.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito Kuge, Naoki Yasuda, Yoshiaki Fukuzumi, Tomoko Fujiwara
  • Patent number: 8742488
    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Kil-Su Jeong, Hansoo Kim, Youngwoo Park
  • Patent number: 8741761
    Abstract: Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Byungkwan You, Youngwoo Park, Kwang Soo Seol
  • Patent number: 8664062
    Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Memory Company
    Inventors: Yung-Chang Lin, Nan-Ray Wu, Le-Tien Jung
  • Patent number: 8659077
    Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Aritra Dasgupta, Unoh Kwon, Sean M. Polvino
  • Patent number: 8647972
    Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Aritra Dasgupta, Unoh Kwon, Sean M. Polvino
  • Patent number: 8642471
    Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: February 4, 2014
    Assignee: The institute of Microelectronics, Chinese Academy of Science
    Inventors: Haizhou Yin, Jun Luo, Huilong Zhu, Zhijiong Luo
  • Patent number: 8642459
    Abstract: A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Martin Poelzl
  • Patent number: 8633569
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 21, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Publication number: 20140008720
    Abstract: A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicants: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Ruilong Xie, Pranatharthi Haran Balasubramanian
  • Patent number: 8592312
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Publication number: 20130286516
    Abstract: Protecting a gate dielectric is achieved with a gate dielectric protection circuit coupled to a transistor at risk. The protection circuit is activated to reduce the voltage across the gate dielectric (VDIFF) to below its breakdown voltage (VBD). The protection circuit is activated when an ESD event is detected. The protection circuit provides a protection or ESD bias to reduce VDIFF below VBD.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Manjunatha Govinda PRABHU, Mahadeva Iyer NATARAJAN, Da-Wei LAI, Ryan SHAN
  • Patent number: 8558299
    Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal nitride film layer on the conductive film layer, a silicon-containing film layer on the refractory metal nitride film layer, and a tungsten film layer on the silicon-containing film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 15, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yong Cao, Xianmin Tang, Srinivas Gandikota, Wei D. Wang, Zhendong Liu, Kevin Moraes, Muhammad M. Rasheed, Thanh X. Nguyen, Ananthkrishna Jupudi
  • Publication number: 20130228928
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a second conductive layer, a second insulating layer, a tubular semiconductor pillar, an insulating film and an occlusion film. The second conductive layer is provided on the stacked body. The second insulating layer is provided on the second conductive layer. The tubular semiconductor pillar is provided in such a manner as to pass through the second insulating layer, the second conductive layer and the stacked body. The insulating film is provided between the semiconductor pillar, and the second insulating layer, the second conductive layer and the stacked body. The occlusion film occludes the tube in a lower portion of the portion passing through the second insulating layer in the semiconductor pillar. The tube below the occlusion film in the semiconductor pillar is an air gap.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhito KUGE, Naoki Yasuda, Yoshiaki Fukuzumi, Tomoko Fujiwara
  • Publication number: 20130224952
    Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
  • Patent number: 8519489
    Abstract: An embodiment relates a method comprising creating a reversible change in an electrical property by adsorption of a gas by a composition, wherein the composition comprises a noble metal-containing nanoparticle and a single walled carbon nanotube. Another embodiment relates to a method comprising forming a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube and forming a device containing the said composition. Yet another method relates to a device comprising a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube on a silicon wafer, wherein the composition exhibits a reversible change in an electrical property by adsorption of a gas by the composition.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 27, 2013
    Assignee: Indian Institute of Technology Madras
    Inventors: Pradeep Thalappil, Chandramouli Subramaniam
  • Patent number: 8507355
    Abstract: A method of manufacturing high performance metal-oxide-metal capacitor device that resolves problems with implementing high capacitance in the metal-oxide-metal region by filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and filling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 13, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Youcun Hu, Lei Li, Chaos Zhang, Feng Ji, Yuwen Chen
  • Patent number: 8471367
    Abstract: A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first barrier layer formed in the second oxide film and connected to the pad electrode, a silicide portion formed between the contact electrode and a through-hole electrode layer and connected to the contact electrode and the first barrier layer, a via hole extending from a back surface of the semiconductor substrate to reach the silicide portion and the second oxide film, a third oxide film formed on a sidewall of the via hole and on the back surface of the semiconductor substrate, and a second barrier layer (H) and a rewiring layer formed inside the via hole and on the back surface of the semiconductor substrate and connected to the silicide portion.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Daishiro Saito, Takayuki Kai, Takafumi Okuma, Hitoshi Yamanishi
  • Patent number: 8470681
    Abstract: A resistor with improved switchable resistance includes a first electrode, a second electrode, and an insulating dielectric structure between the first and second electrodes. The insulating dielectric structure includes a confined conductive region providing a first resistance state and a second resistance state; the resistance state of the confined conductive region being switchable between the first and second resistance states by a control signal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christophe P. Rossel, Michel Despont
  • Publication number: 20130157451
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Publication number: 20130146950
    Abstract: A semiconductor device and manufacture method thereof include a silicide material formed on a source region and a drain region on opposite sides of a gate, wherein the gate having sidewalls on both side surfaces is formed on a substrate. The gate has a first sidewall spacer and a second sidewall spacer on each sidewall, the first spacer has a horizontal portion and a vertical portion, the horizontal portion is located between the second sidewall spacer and the substrate, the vertical portion is located between the second sidewall spacer and the sidewalls. A protecting layer is selectively deposited on the silicide material.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 13, 2013
    Applicant: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: FENGLIAN LI
  • Patent number: 8450191
    Abstract: Methods of forming polysilicon layers are described. The methods include forming a high-density plasma from a silicon precursor in a substrate processing region containing the deposition substrate. The described methods produce polycrystalline films at reduced substrate temperature (e.g. <500° C.) relative to prior art techniques. The availability of a bias plasma power adjustment further enables adjustment of conformality of the formed polysilicon layer. When dopants are included in the high density plasma, they may be incorporated into the polysilicon layer in such a way that they do not require a separate activation step.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: May 28, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Xiaolin Chen, Young S. Lee
  • Patent number: 8436405
    Abstract: The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a power line, and each cell of a second subset of ROM cells has a source electrically isolated.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Publication number: 20130075913
    Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Xiao Hu Liu, Thomas L. McDevitt, Gary L. Milo, William J. Murphy
  • Publication number: 20130043597
    Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ming-Chuan Yang, Zengtao T. Liu, Vishal Sipani
  • Publication number: 20130040460
    Abstract: A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.
    Type: Application
    Filed: September 6, 2012
    Publication date: February 14, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Hyungsuk Alexander Yoon, Mikhail Korolik, Fritz C. Redeker, John M. Boyd, Yezdi Dordi
  • Patent number: 8367508
    Abstract: A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Xinhui Wang, Keith Kwong Hon Wong
  • Publication number: 20130020619
    Abstract: A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.
    Type: Application
    Filed: September 27, 2012
    Publication date: January 24, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Hynix Semiconductor Inc.
  • Patent number: 8354342
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: January 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Geun Oh, Seung-Joon Jeon, Jin-Ku Lee, Mi-Ri Lee, Bong-Seok Jeon
  • Patent number: 8354719
    Abstract: A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 15, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Kisik Choi, Robert J. Miller
  • Patent number: 8354727
    Abstract: A semiconductor device of high reliability and element-integrating performance, has a substrate (silicon substrate), a first trench made in the silicon substrate, a passive element layer buried in the first trench, and a first insulating film (silicon nitride film) arranged between the first trench and the passive element layer. The passive element layer projects upwardly relative to the substrate, and so too preferably the adjacent insulating film. An active element is formed such that its gate electrode, which is preferably fully silicided, has an upper end at a level higher than the upper surface of the passive element film.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Satoru Muramatsu
  • Publication number: 20130012015
    Abstract: A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Applicant: AMKOR TECHNOLOGY, INC.
    Inventors: Kwang Sun Oh, Dong Hee Lee, Dong In Kim, Bae Yong Kim, Jin Woo Park
  • Publication number: 20120326167
    Abstract: A silicon carbide substrate has a substrate surface. A gate insulating film is provided to cover a part of the substrate surface. A gate electrode covers a part of the gate insulating film. A contact electrode is provided on the substrate surfaces, adjacent to and in contact with the gate insulating film, and it contains an alloy having Al atoms. Al atoms do not diffuse from the contact electrode into a portion of the gate insulating film lying between the substrate surface and the gate electrode.
    Type: Application
    Filed: October 19, 2011
    Publication date: December 27, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hideto Tamaso
  • Publication number: 20120322246
    Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung WANG, Hsien-Chin LIN, Yuan-Ching PENG, Chia-Pin LIN, Fan-Yi HSU, Ya-Jou HSIEH
  • Publication number: 20120319198
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20120313187
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Baars, Till Schloesser, Frank Jakubowski
  • Publication number: 20120309144
    Abstract: In some embodiments of the inventive subject matter, methods include forming an oxide layer on a semiconductor substrate, injecting nitrogen into the oxide layer to form a nitrogen injection layer and to change the oxide layer to an oxynitride layer, removing a part of the oxynitride layer to leave a portion of the oxynitride layer in a first area and expose the nitrogen injection layer in a second area and forming an insulating layer comprising a portion on the portion of the oxynitride layer in the first area and a portion on the nitrogen injection layer in the second area. The insulating layer may have a higher dielectric constant than the oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: December 6, 2012
    Inventors: Jin-ho Do, Moon-han Park, Weon-hong Kim, Kyung-il Hong
  • Publication number: 20120299099
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu