Through-implantation (epo) Patents (Class 257/E21.337)
  • Patent number: 9972539
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 15, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9412851
    Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
  • Patent number: 9373512
    Abstract: An apparatus and method for performing ion implantation while minimizing and/or repairing amorphization of the substrate material. The process comprises exposing a substrate to an ion beam and either concurrently or promptly following the ion implantation using a laser to anneal the surface. In addition, a laser may be utilized to preheat the substrate prior to ion implantation. The laser heats the substrate to a temperature that does not cause the resist layer to be damaged. By utilizing a laser to heat the substrate from the top surface the resist is not damaged allowing for the use of photo resist material.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 21, 2016
    Assignee: GlobalFoundries, Inc.
    Inventor: Nicolas Breil
  • Patent number: 9373713
    Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 21, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Yao-Feng Huang, Hsiang-Ting Hung, Chwan-Ying Lee
  • Patent number: 8889503
    Abstract: Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventor: Kenji Yoneda
  • Patent number: 8785306
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Patent number: 8759938
    Abstract: A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
  • Patent number: 8709927
    Abstract: Methods of implanting dopant ions in a substrate include depositing a sacrificial material on a substrate. Dopant ions are implanted into the substrate while sputtering the sacrificial material, without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after the implanting of the dopant ions. Some methods include forming a sacrificial material over a substrate and implanting dopant ions into the substrate while removing substantially all the sacrificial material from the substrate. Substantially no sputtering of the substrate occurs during the implanting of the dopant ions. Methods of doping a substrate include implanting dopant ions into a substrate having a sacrificial material thereon and sputtering the sacrificial material while implanting the dopant ions without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after implanting the dopant ions.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Li Li
  • Patent number: 8629026
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8580662
    Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masakuni Shimizu
  • Patent number: 8563381
    Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8492221
    Abstract: A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 23, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8383498
    Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3, the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 26, 2013
    Assignee: IMEC
    Inventor: Simone Severi
  • Patent number: 8329566
    Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 11, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Wenwu Wang
  • Patent number: 8324088
    Abstract: Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: December 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Li Li
  • Patent number: 8133781
    Abstract: A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconductor substrate. Straggle of the implanted ions form a doped region that laterally extends beyond a horizontal cross-sectional area of the opening. A deep trench is formed by performing an anisotropic etch of a semiconductor material underneath the opening to a depth above a deep end of an implanted region. Ion implantation steps and anisotropic etch steps are alternately employed to extend the depth of the doped region and the depth of the deep trench, thereby forming a doped region around a deep trench that has narrow lateral dimensions. The doped region can be employed as a buried plate for a deep trench capacitor.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Geng Wang
  • Patent number: 8110487
    Abstract: By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 7, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Christoph Schwan, Kerstin Ruttloff
  • Patent number: 8105924
    Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Publication number: 20110284992
    Abstract: The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.
    Type: Application
    Filed: September 19, 2010
    Publication date: November 24, 2011
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 7968401
    Abstract: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: June 28, 2011
    Inventors: Martin A. Hilkene, Kartik Santhanam, Yen B. Ta, Peter I. Porshnev, Majeed A. Foad
  • Patent number: 7939418
    Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 10, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Yong-sun Sohn, Min Yong Lee
  • Patent number: 7935618
    Abstract: Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Li Li
  • Patent number: 7915128
    Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Wen Chen, Fu-Hsin Chen, Ming-Ren Tsai, William Wei-Yuan Tien
  • Patent number: 7838927
    Abstract: A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 23, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Ferruccio Frisina, Simone Rascuna
  • Patent number: 7825043
    Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Patent number: 7772098
    Abstract: On one face of a semiconductor wafer 1 having a first face (principal face) 1a and a second face (rear face) 1b, a protection film 2 is formed. When allowing the semiconductor wafer 1 to be attracted onto an attracting face of an electrostatic chuck 6 which is heated to 400° C. or more, the semiconductor wafer 1 is attracted onto the attracting face via the protection film 2. While heating the semiconductor wafer 1 to 400° C. or more, an ion implantation is performed for the face of the semiconductor wafer 1 on which the protection film 2 is not formed. Thereafter, the protection film 2 is removed from the semiconductor wafer 1.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Osamu Kusumoto, Chiaki Kudou, Kunimasa Takahashi
  • Patent number: 7759208
    Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Christian Lavoie, Ahmet S. Ozcan, Donald R. Wall
  • Patent number: 7682888
    Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Lee, Tetsuji Ueno, Hwa-Sung Rhe
  • Patent number: 7662705
    Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: February 16, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
  • Publication number: 20090261348
    Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.
    Type: Application
    Filed: May 9, 2006
    Publication date: October 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi
  • Patent number: 7538003
    Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Min Yong Lee, Yong Soo Joung
  • Patent number: 7534667
    Abstract: A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Brian J. Greene, John J. Ellis-Monaghan
  • Patent number: 7531435
    Abstract: In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 12, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Youichi Momiyama
  • Publication number: 20080272409
    Abstract: A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 6, 2008
    Inventors: Sachin R. Sonkusale, Weimin Zhang, Ashok K. Kapoor
  • Patent number: 7402495
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive type; and first to third ion implantation processes sequentially executed for controlling threshold voltages corresponding to each transistor formed on the semiconductor substrate the first semiconductor region, and the second semiconductor region respectively. The first ion implantation process is executed in a high-threshold low-voltage transistor forming region of the first semiconductor region after forming the first semiconductor region. The second ion implantation process is executed in a high-threshold low-voltage transistor forming region of the second semiconductor region.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minori Kajimoto, Mitsuhiro Noguchi
  • Patent number: 7384834
    Abstract: A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: June 10, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Katsuhiro Mitsuda, Mitsuharu Honda, Akira Iizuka
  • Patent number: 7319061
    Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
  • Publication number: 20080001217
    Abstract: An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoshiya Kawashima
  • Patent number: 7282416
    Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
  • Patent number: 7247547
    Abstract: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Oleg Gluschenkov, Chun-Yung Sung
  • Patent number: 7223663
    Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: May 29, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hak-Dong Kim
  • Patent number: 7217136
    Abstract: A printed circuit board having right-angled trace and a method for making the right-angled trace is to apply semi-conductor material and form an interface with a P-type semi-conductive layer and a N-type semi-conductive layer. The semi-conductive right-angled interface does not reflect signals transmitting from the first line portion to the second line portion and via the right-angled portion so as to reduce signal reflection interference. The right-angled line arrangement also shortens the connection distance and reduces the circuit board dimensions.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: May 15, 2007
    Assignee: Mitac International Corp.
    Inventor: Che-fu Chang
  • Patent number: 7199030
    Abstract: An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatment-based stress between the silicon nitride film and the silicon substrate.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: April 3, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Satoshi Ikeda, Yutaka Kamata, Ikuo Kurachi, Norio Hirashita
  • Patent number: 7192789
    Abstract: A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to the wafer, performing a thermal treatment process, removing the barrier layer, and measuring a physical property of the wafer. The measured physical property of the wafer can be used to ascertain the status of the ion implanter. For instance, the measured physical property can be used to determine whether the ion implanter has problems when the energy or concentration of the implanted ions is changed.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: March 20, 2007
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chun Te Lin, Chih Sheng Yang, Hong Zhi Lee, Ta-Te Chen
  • Patent number: 7157357
    Abstract: Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film pattern stacked sequentially; forming an ion implantation buffer film on an exposed surface of the semiconductor substrate and the gate conductive film pattern; performing a first ion implantation process for injecting fluorine ions into the semiconductor substrate; performing a second ion implantation process for implanting p-type halo ions into the semiconductor substrate; performing a third ion implantation process for implanting n-type impurity ions into the semiconductor substrate; and diffusing the p-type halo ions and the n-type impurity ions using a thermal process.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: January 2, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hak-Dong Kim
  • Patent number: 7135392
    Abstract: A method for forming P-N junctions in a semiconductor wafer includes ion implanting dopant impurities into the wafer and annealing the wafer using a thermal flux laser annealing apparatus that includes an array of semiconductor laser emitters arranged in plural parallel rows extending along a slow axis, plural respective cylindrical lenses overlying respective ones of the rows of laser emitters for collimating light from the respective rows along a fast axis generally perpendicular to the slow axis, a homogenizing light pipe having an input face at a first end for receiving light from the plural cylindrical lenses and an output face at an opposite end, the light pipe comprising a pair of reflective walls extending between the input and output faces and separated from one another along the direction of the slow axis, and scanning apparatus for scanning light emitted from the homogenizing light pipe across the wafer in a scanning direction parallel to the fast axis.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: November 14, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Bruce E. Adams, Dean Jennings, Abhilash J. Mayur, Vijay Parihar, Joseph M. Ranish