Of Electrically Active Species (epo) Patents (Class 257/E21.341)
  • Patent number: 8853065
    Abstract: A method of fabricating a semiconductor device includes selecting an element for implanting into a substrate. The element has at least a first isotope and a second isotope. At least one implant contaminant is identified as having a particle weight that is substantially identical to an atomic weight of the first isotope of the element. As such, ions of the second isotope of the element are selectively implanted into a region of the substrate. The second isotope has an atomic weight that is different from the particle weight of the at least one implant contaminant. For example, the selected element may be silicon (Si), the implant contaminant may be nitrogen (N2), the first isotope having the substantially identical atomic weight may be silicon-28, and the second isotope having the different atomic weight may be silicon-29. Related methods, apparatus, and devices are also discussed.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 7, 2014
    Assignee: Cree, Inc.
    Inventor: Alexander Suvorov
  • Patent number: 8461632
    Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: June 11, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noriaki Tsuchiya, Yoichiro Tarui
  • Patent number: 8105889
    Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 31, 2012
    Assignee: Cree, Inc.
    Inventors: R. Peter Smith, Scott T. Sheppard
  • Publication number: 20070269966
    Abstract: A method of fabricating a semiconductor device includes selecting an element for implanting into a substrate. The element has at least a first isotope and a second isotope. At least one implant contaminant is identified as having a particle weight that is substantially identical to an atomic weight of the first isotope of the element. As such, ions of the second isotope of the element are selectively implanted into a region of the substrate. The second isotope has an atomic weight that is different from the particle weight of the at least one implant contaminant. For example, the selected element may be silicon (Si), the implant contaminant may be nitrogen (N2), the first isotope having the substantially identical atomic weight may be silicon-28, and the second isotope having the different atomic weight may be silicon-29. Related methods, apparatus, and devices are also discussed.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 22, 2007
    Inventor: Alexander Suvorov