Abstract: A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type.

Abstract: A fabrication method of a trench power semiconductor structure is provided. First, a substrate with a first epitaxial layer is provided. Then, a dielectric layer is formed on the first epitaxial layer. A shielding layer is formed on the dielectric layer. Next, a portion of the shielding and the dielectric layers are removed to form a shielding structure and a dielectric structure on the first epitaxial layer, wherein the shielding structure is stacked on the dielectric structure. A selective epitaxial growth technique is utilized to form a second epitaxial layer surrounding the dielectric and the shielding structures on the exposed surface of the first epitaxial layer and the second epitaxial layer. Afterward, the shielding structure is removed to form a trench on the dielectric structure. A gate oxide layer is further formed on the inner surface of the trench. Lastly, a conducting structure is formed in the trench.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

Abstract: A method for forming a highly integrated semiconductor device having multiplayer conductive lines is presented. The method includes the operations of forming, etching, burying and forming. The first forming operation includes forming a line-type conductive layer on a semiconductor substrate including a buried gate to expose the gate. The etching operation includes etching the conductive layer to expose at least a region between one side of an active area defined in the semiconductor substrate and an opposite side of the neighboring active area, both the active areas being arranged next to each other in a major axis direction of the gate. The burying operation includes burying a first insulating film in the etched line-type conductive layer. The second forming operation includes forming a bit line passing through the center of the active area in a direction perpendicular to the major axis direction of the gate.

Abstract: A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region; a second semiconductor region having a side face and a lower face, and the faces surrounded by the first semiconductor region; a third semiconductor region provided between the second semiconductor region and the first semiconductor region; a fourth semiconductor region being in contact with an outer side face of the first semiconductor region; a plurality of first electrodes being in contact with the second semiconductor region, the third semiconductor region, and the first semiconductor region via an insulating film; a plurality of pillar areas extending from the third semiconductor region toward the fourth semiconductor region, each of the plurality of pillar areas being provided between adjacent ones of the plurality of first electrodes. An impurity density of each of the pillar areas and an impurity density of the third semiconductor region is substantially the same.

Abstract: A nanodevice is disclosed. The nanodevice comprises: a drain region, a source region opposite to the drain region and being separated therefrom at least with a trench, and a gate region, isolated from the drain and the source regions and from the trench. The trench has a height which is between 1 nm and 30 nm.

Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.

Abstract: An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.

Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

Abstract: A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds.

Abstract: A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.

Abstract: A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.

Abstract: A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract: A semiconductor device includes a reverse-conducting insulated gate bipolar transistor (IGBT), wherein the thickness of the semiconductor layer underlying the diode region of the device is thinner than the thickness of the semiconductor layer underlying the IGBT portion of the device. In one aspect, the semiconductor layer is a continuous layer, and trenches defining the anodes in the diode region extend further inwardly of the semiconductor layer than does the base regions of the IGBT portion of the device.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type which is provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type which is selectively provided on a surface of the second semiconductor layer, an insulating film which is provided to cover an inner wall of a trench running into the first semiconductor layer from an upper face of the third semiconductor layer, a field plate electrode which is provided in a lower portion of the trench, a gate electrode which is provided on the field plate electrode via the insulating film, and a fourth semiconductor layer of the second conductivity type which is provided at least in a region direct below the trench, and comes into contact with the insulating film.

Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate, wherein the patterned semiconductor layer defines first and second trenches. The electronic device can also include a first conductive structure within the first trench, a gate electrode within the first trench and overlying the first conductive structure, a first insulating member within the second trench, and a second conductive structure within the second trench. The second conductive structure can include a first portion and a second portion overlying the first portion, the first insulating member can be disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and the second portion of the second conductive structure can contact the patterned semiconductor layer at a Schottky region. Processes of forming the electronic device can take advantage of integrating formation of the Schottky region into a contact process flow.

Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

Abstract: A semiconductor device includes a trench region extending into a drift zone of a semiconductor body from a surface. The semiconductor device further includes a dielectric structure including a first step and a second step along a lateral side of the trench region. The semiconductor device further includes an auxiliary structure of a first conductivity type between the first step and the second step, a gate electrode in the trench region and a body region of a second conductivity type other than the first conductivity type of the drift zone. The auxiliary structure adjoins each one of the drift zone, the body region and the dielectric structure.

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer.

Abstract: According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.

Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.

Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: A semiconductor device includes a semiconductor body having a first surface defining a vertical direction and a source metallization arranged on the first surface. In a vertical cross-section the semiconductor body further includes: a drift region of a first conductivity type; at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization; a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region, and a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and includes at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer.

Abstract: Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped.

Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract: A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.

Abstract: A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.