Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.

Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: A method of making a semiconductor device includes forming a split gate memory gate structure on a memory region of a substrate, and protecting the split gate memory gate structure by depositing protective layers over the memory region including the memory gate structure and over a logic region of the substrate. The protective layers include a material that creates a barrier to diffusion of metal. The protective layers are retained over the memory region while forming a logic gate in the logic region. The logic gate includes a high-k dielectric layer and a metal layer. A spacer material is deposited over the logic gate. Spacers are formed on the memory gate structure and the logic gate. The spacer on the logic gate is formed of the spacer material and the spacer on the memory gate structure is formed with one of the protective layers.

Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.

Abstract: Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.

Abstract: A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, a first charge trap layer on the interface insulating layer, and a second charge trap layer on the first charge trap layer, and a trap level of the second charge trap layer is lower than a trap level of the first charge trap layer.

Abstract: A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side.

Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.

Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.

Abstract: In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed.

Abstract: A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

Abstract: Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks.

Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.

Abstract: A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure.

Abstract: A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.

Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.

Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.

Abstract: An improved gate structure is provided whereby the gate structure is defined by a trench, the trench having a first oxide layer and a second oxide layer. The invention also provides methods for fabricating the gate structure of the invention defined by a trench having a first oxide layer and a second oxide layer.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

Abstract: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.

Abstract: An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer.

Abstract: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.

Abstract: A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

Abstract: Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.

Abstract: A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.

Abstract: A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.

Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.