With Asymmetry In Channel Direction, E.g., High-voltage Lateral Transistor With Channel Containing Layer, E.g., P-base (epo) Patents (Class 257/E21.427)
  • Patent number: 10636876
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to devices with channel extension regions and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; and a channel below the gate structure, the channel comprising: a first channel region, adjacent to the source region; and a second channel region, adjacent to the drain region and comprising a lower threshold voltage than the first channel region.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lars Müller-Meskamp, Luca Pirro, Edward J. Nowak
  • Patent number: 10615159
    Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10593795
    Abstract: An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Seetharaman Sridhar
  • Patent number: 10586735
    Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: March 10, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Patent number: 10411098
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: September 10, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Chih-Wei Chen, Heng-Kuang Lin
  • Patent number: 10374041
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yulong Li, Paul M. Solomon, Siyuranga Koswatta
  • Patent number: 10312365
    Abstract: Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 4, 2019
    Assignee: Avago Technologies International Sales PTE. Limited
    Inventors: Qing Liu, Akira Ito, Shom Surendran Ponoth
  • Patent number: 10276710
    Abstract: A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 30, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shin-Hung Li, Chang-Po Hsiung
  • Patent number: 10147800
    Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Liang Liu, Shih-Yin Hsiao, Ching-Chung Yang
  • Patent number: 10068896
    Abstract: An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Yen, Po-Ya Lai, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 10062780
    Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10043890
    Abstract: A method is provided for forming spacers of a gate of a field effect transistor, the gate including flanks and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer covering the gate; after the step of forming, at least one step of modifying the dielectric layer by putting the dielectric layer into presence of a plasma creating a bombarding of light ions; and at least one step of removing the modified dielectric layer including a dry etching performed by putting the modified dielectric layer into presence of a gaseous mixture including at least one first component with a hydrofluoric acid base that transforms the modified dielectric layer into non-volatile residue, and removing the non-volatile residue via a wet clean performed after the dry etching or a thermal annealing of sublimation performed after or during the dry etching.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 7, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Pollet, Nicolas Posseme
  • Patent number: 10014206
    Abstract: An integrated circuit (IC) including at least one transistor having a metal-oxide-semiconductor (MOS) gate includes a substrate having a semiconductor surface. The transistor includes at least one trench isolation region in the semiconductor surface. Local oxidation of silicon (LOCOS) regions extend from within the semiconductor surface inside the trench isolation region defining a first LOCOS-free region and at least a second LOCOS-free region. A gate electrode is between the first LOCOS-free region and second LOCOS-free region including over a flat portion of a first of the LOCOS regions as its gate dielectric (LOCOS gate oxide). A first doped region is in the first LOCOS-free region and a second doped region is in the second LOCOS-free region on respective sides of the gate electrode both doped a first dopant type. A recessed channel region for the transistor is between the first and second doped regions under the LOCOS gate oxide.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ming-Yeh Chuang
  • Patent number: 9773796
    Abstract: A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Hyun Lee, Jin-Kyu Kim
  • Patent number: 9691893
    Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 27, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
  • Patent number: 9633995
    Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 9543299
    Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: January 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Sameer P. Pendharkar, Henry Litzmann Edwards
  • Patent number: 9520467
    Abstract: The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 9502557
    Abstract: An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: November 22, 2016
    Assignee: Coolstar Technology, Inc.
    Inventors: Shuming Xu, Wenhua Dai
  • Patent number: 9373712
    Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 21, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhong-Sheng Wang, Jiaw-Ren Shih
  • Patent number: 9336346
    Abstract: A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer that forms base cells within a plurality of logic standard cells in a CMOS process technology that includes conventional symmetric CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length exceeding 1.5 times the minimum gate length of the symmetric CMOS transistors. Regions defined by electrical junctions directly adjacent to the gate of the asymmetric transistors are formed by an implant mask exposing an area of the wafer on the source side of the transistor to receive the junction implant of the symmetric CMOS transistors with a higher threshold voltage while shielding the drain area, and a further implant mask exposing an area of the wafer on the drain side of the transistor to receive the junction implant of the symmetric CMOS transistors with a lower threshold voltage while shielding the source area.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 10, 2016
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Rainer Herberholz
  • Patent number: 9000517
    Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Tung-Yang Lin, Ruey-Hsin Liu
  • Patent number: 8921170
    Abstract: Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Jun Liu, Albert Ratnakumar, Mark T. Chan, Irfan Rahim
  • Patent number: 8872281
    Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Lie, James S. Nakos, Bradley A. Omer, Robert M. Rassel, David C. Sheridan
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8828809
    Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Alfio Guarnera
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8786020
    Abstract: Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventor: Michael Andrew Smith
  • Patent number: 8729629
    Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 20, 2014
    Assignees: Atmel Rousset S.A.S., Laas-CNRS
    Inventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
  • Patent number: 8698243
    Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8674729
    Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masaharu Yamaji
  • Patent number: 8674455
    Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 18, 2014
    Inventors: Kensuke Okonogi, Kazuhiro Nojima, Kiyonori Oyu
  • Patent number: 8669149
    Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: March 11, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Hung-Shern Tsai
  • Patent number: 8664728
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: March 4, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 8643137
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 8633075
    Abstract: A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Patent number: 8629026
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8592901
    Abstract: A metal oxide semiconductor field transistor including a gate electrode, a gate dielectric layer, a source region, a drain region, and a top doped region are provided. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounded the drain region. The gate electrode is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate electrode and the substrate. The top doped region of a second conductivity type is located in the substrate between the gate electrode and the drain region. The top doped region includes at least three regions. Each of the three regions has a dopant concentration gradient and a concentration gradually decreased from a region adjacent the gate electrode to a region adjacent the drain region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: November 26, 2013
    Assignee: Nuvoton Technology Corporation
    Inventors: Gene Sheu, MD Imran Siddiqui, Abijith Prakash, Shao-Ming Yang, Jung-Ruey Tsai
  • Patent number: 8574991
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Patent number: 8569138
    Abstract: A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 29, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Hee Bae Lee, Choul Joo Ko
  • Patent number: 8524563
    Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: September 3, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8410549
    Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Jeng-Jiun Yang, William D. French, Sandeep R. Bahl, D. Courtney Parker
  • Patent number: 8405148
    Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: March 26, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8389341
    Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yi Huang, Puo-Yu Chiang, Ruey-Hsin Liu, Shun-Liang Hsu, Chyi-Chyuan Huang, Fu-Hsin Chen, Eric Huang
  • Patent number: 8377755
    Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8362560
    Abstract: Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pranita Kulkarni, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz
  • Patent number: 8338265
    Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
  • Patent number: 8299548
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Tsubasa Yamada, Jun Morioka, Koji Kimura
  • Patent number: 8298897
    Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 30, 2012
    Assignees: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
  • Patent number: RE44730
    Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 28, 2014
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom