Abstract: Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.

Abstract: An electronic device can include a drain region of a transistor, wherein the drain region has a first conductivity type. The electronic device can also include a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type. The electronic device can further include a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region. The electronic device can still further include a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region.

Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor.

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.

Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask.

Abstract: A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a second well, implanting second conduction type impurities into the second well to form an impurity region, forming a gate on the semiconductor substrate, and implanting second conduction type impurities to form a drain region in the impurity region on one side of the gate.

Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

Abstract: An electronic device includes a semiconductor substrate of a first conductivity type and a drain layer adjacent the semiconductor substrate and having a plurality of drains. The drain layer includes a first semiconductor layer of the first conductivity type adjacent the semiconductor substrate, and at least one second semiconductor layer of a second conductivity type adjacent the first semiconductor layer. Moreover, a plurality of first column regions of the first conductivity type extends through the at least one second semiconductor layer to contact the first semiconductor layer. A plurality of second column regions of the second conductivity type delimits the plurality of first column regions. Furthermore, a plurality of body regions of the second conductivity type are adjacent respective ones of the plurality of second column regions.

Abstract: A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: A DC-DC boost converter in multi-die package is proposed having an output Schottky diode and a low-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a single die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the single die pad via an insulating die bond. Alternatively, the single die pad is grounded. The vertical MOSFET is a top drain vertical N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the single die pad. The PRC is attached atop the single die pad via a standard conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.

Abstract: A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.

Abstract: In a power semiconductor device including a semiconductor substrate of a first conductivity type, a source region of a second conductivity type formed in a surface portion of the semiconductor substrate, and a drain drift region of the second conductivity type formed in the surface portion of the semiconductor substrate, the drain drift region being apart from the source region, a drain region of the second conductivity type is formed in a surface portion of the drain drift region. The drain region has a larger impurity concentration than the drain drift region. A drain buried region of the second conductivity type is formed immediately below the drain region in the drain drift region. The drain buried region has a larger impurity diffusion region than the drain drift region. A gate insulating layer is formed on the semiconductor substrate between the source region and the drain drift region, and a gate electrode is formed on the gate insulating layer.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.

Abstract: Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

Abstract: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask.

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract: The invention relates to an asymmetric gate electrode and method of manufacturing an asymmetric gate electrode. The method includes: forming a source region and drain region in a substrate; forming a symmetrical gate structure over a channel formed between the source region and the drain region; depositing a material on the substrate and planarizing the material to a top of the symmetrical gate structure; recessing the symmetrical gate structure to below a surface of the material; forming spacers in the recess; protecting one edge of the spacer while etching another edge of the spacer to remove a portion thereof; and recessing the symmetrical gate structure on a side closest to the source region while the another edge of the spacer protects the symmetrical gate structure on a side closest to the drain region to form an asymmetrical gate electrode.

Abstract: An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.

Abstract: A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42?) in which adjacent or spaced-apart P (46, 46?) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42?) and is spaced apart from the wells (46, 46?, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42?) between the wells (46?, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42?) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42?) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

Abstract: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.

Abstract: An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.

Abstract: Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a second conductivity type between a channel (78) of a first conductivity type and a drain (74) to inhibit channel hot carrier or direct tunneling degradation of the transistor gate dielectric (64) for high voltage operation. The voltage drop region (80) has more dopants of the first conductivity type and/or fewer dopants of the second conductivity type than does the well (82) so as to shift the high fields away from the transistor gate dielectric (64).

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type semiconductor layer without thermally diffusing an impurity, (b) forming a gate electrode including an edge vicinity region that is aligned with the first region in the horizontal position, and (c) forming a body layer including the first region and a second region that is formed adjacent to the first region and self-aligned with the first region and an edge of the gate electrode by forming the second region with a step of selectively ion-implanting a second conductive type impurity into the first conductive type semiconductor layer without thermally diffusing an impurity.

Abstract: The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n?-type offset drain region, an n-type offset drain region, and an n+-type drain region. A side wall spacer comprising a silicon film is formed via an insulating film on the side wall of the gate electrode over the drain side thereof, and a field plate electrode is formed by this side wall spacer. The field plate electrode does not extend above the gate electrode, and a metal silicide film is formed over the entire upper surface of the gate electrode in the silicide process.

Abstract: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided.

Abstract: A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.