Lateral Single Gate Single Channel Silicon Transistor With Both Lightly Doped Source And Drain Extensions And Source And Drain Self-aligned To Sides Of Gate, E.g., Ldd Mosfet, Ddd Mosfet (epo) Patents (Class 257/E21.435)
  • Patent number: 10242908
    Abstract: Processing methods may be performed to remove unwanted materials from a substrate, such as an oxide footing. The methods may include forming an inert plasma within a processing region of a processing chamber. Effluents of the inert plasma may be utilized to modify a surface of an exposed material on a semiconductor substrate within the processing region of the semiconductor chamber. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 26, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Sean Kang, Jungmin Ko, Oliver Luere
  • Patent number: 9029921
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 8975128
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 10, 2015
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8962406
    Abstract: An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8921174
    Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Qianqian Huang, Zhan Zhan, Yingxin Qiu, Yangyuan Wang
  • Patent number: 8907375
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Sony Corporation
    Inventor: Masashi Yanagita
  • Patent number: 8878310
    Abstract: An integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8877596
    Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Darshana N. Bhagat, Thomas J. Dunbar, Yen Li Lim, Jed H. Rankin, Eva A. Shah
  • Patent number: 8853042
    Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 ? of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Amitabh Jain
  • Patent number: 8846550
    Abstract: The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Eric Shero, Suvi Haukka
  • Patent number: 8809186
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8785286
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Patent number: 8753945
    Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keon-Yong Cheon, Dong-Won Kim, Sung-Man Lim, Sadaaki Masuoka, Yaoqi Dong
  • Patent number: 8735294
    Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 27, 2014
    Assignee: International Rectifier Corporation
    Inventor: Igor Bol
  • Patent number: 8704307
    Abstract: Disclosed herein is a device for electrostatic discharge protection. According to the present invention, the device for electrostatic discharge protection comprises a semiconductor substrate, a plurality of element isolation films formed in predetermined regions on the semiconductor substrate, a gate formed in a predetermined region on the semiconductor substrate between the element isolation films, a well pick-up region formed in a predetermined region on the semiconductor substrate between the element isolation films, a source formed in a predetermined region on the semiconductor substrate between the element isolation film and the gate, and drains of a triple structure, which are formed in a predetermined region on the semiconductor substrate between the gate and the element isolation film. Furthermore, the gate, the well pick-up region and the source are connected to a ground line, and the drain is connected to a power line. Accordingly, a stable and good ESD protection performance can be implemented.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: April 22, 2014
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Kil Ho Kim
  • Patent number: 8698209
    Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: April 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8685810
    Abstract: A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell has at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The first power layer has conductive lines in at least two different directions and the at least one second power layer has conductive lines in at least two different directions. The method further includes filling a target area in the power layout by at least one unit power cell to implement at least one power cell.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Chieh Yang
  • Patent number: 8664714
    Abstract: A power MOSFET includes an epitaxy substrate, conductive trenches, well regions and a dielectric layer. The power MOSFET further has at least one termination structure including at lest one of the conductive trenches, some of the well regions within a termination area and mutually insulated by the conductive trench, a field plate, a contact plug and a heavily-doped region. The field plate including a plate metal and the dielectric layer is on the well regions and the conductive trench within the termination area. The contact plug penetrates through the dielectric layer and connects the plate metal and one of the well regions, so the plate metal has equal potential with the connected well region through the contact plug. The well regions and the conductive trench are electrically coupled to the plate metal by the dielectric layer. The heavily-doped region is between the contact plug and the connected well region.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 4, 2014
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Patent number: 8664060
    Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
  • Patent number: 8664068
    Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper
  • Patent number: 8659023
    Abstract: A monocrystalline layer having a first lattice constant on a monocrystalline substrate having a second lattice constant at least in a near-surface region, wherein the second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8633521
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 21, 2014
    Assignee: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8629495
    Abstract: The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 14, 2014
    Assignee: NXP, B.V.
    Inventor: Lukas Frederik Tiemeijer
  • Patent number: 8604527
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8604530
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 10, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8592902
    Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Texas Instrument Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8592268
    Abstract: An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
  • Patent number: 8586475
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 8569136
    Abstract: A manufacturing method of a semiconductor device is provided which can improve the performance of the semiconductor device. Ion implantation is applied to nMIS regions 1A and 1B and pMIS regions 1C and 1D of a semiconductor substrate 1 with offset spacers formed over sidewalls of gate electrodes GE1, GE2, GE3, and GE4 to thereby form extension regions for source and drain. In this case, a different photoresist pattern is used for each of the nMIS regions 1A and 1B and the pMIS regions 1C and 1D to individually perform the corresponding ion implantation. Every time the photoresist pattern is re-created, the offset spacer is also re-created.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronic Corporation
    Inventor: Itaru Kanno
  • Patent number: 8551842
    Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Onizawa
  • Patent number: 8541824
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: September 24, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 8525258
    Abstract: The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 3, 2013
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Ying-Shiou Lin
  • Patent number: 8513719
    Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Martin H. Manley
  • Publication number: 20130200470
    Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
  • Patent number: 8492229
    Abstract: An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: July 23, 2013
    Inventors: Albert Birner, Qiang Chen
  • Patent number: 8486822
    Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 16, 2013
    Assignee: SK hynix Inc.
    Inventor: Byung Ho Nam
  • Patent number: 8476139
    Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Jing Wang
  • Patent number: 8460976
    Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8426287
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 23, 2013
    Assignee: Sony Corporation
    Inventor: Masashi Yanagita
  • Patent number: 8421205
    Abstract: A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Chieh Yang
  • Patent number: 8420490
    Abstract: The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: April 16, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8390063
    Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 5, 2013
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Xiangdong Chen
  • Patent number: 8377755
    Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8372705
    Abstract: CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Lahir Shaik Adam, Sanjay C Mehta, Balasubramanian S Haran, Bruce B. Doris
  • Publication number: 20130023094
    Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsi YEH, Hsien-Hsin LIN, Ying-Hsueh CHANG CHIEN, Yi-Fang PAI, Chi-Ming YANG, Chin-Hsiang LIN
  • Publication number: 20130015533
    Abstract: A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shiang-Bau WANG
  • Patent number: 8354699
    Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 15, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Howard E. Rhodes
  • Patent number: 8304831
    Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Zhu, Lee-Wee Teo, Han-Guan Chew, Harry Hak-Lay Chuang