Using Self-aligned Silicidation, I.e., Salicide (epo) Patents (Class 257/E21.438)
  • Patent number: 12040375
    Abstract: A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Liang Cheng
  • Patent number: 11769819
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. An atomic concentration of the dopant decreases along a direction from an inner surface of the spacer element adjacent to the metal gate stack towards an outer surface of the spacer element.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
  • Patent number: 11482610
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Patent number: 11437493
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: September 6, 2022
    Inventors: Chun Hsiung Tsai, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Patent number: 11398383
    Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 26, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Chun-Sheng Lu
  • Patent number: 11393914
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: July 19, 2022
    Inventors: Chun Hsiung Tsai, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Patent number: 11367778
    Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
  • Patent number: 11282920
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Lu Lin, Che-Chen Wu, Chia-Lin Chuang, Yu-Ming Lin, Chih-Hao Chang
  • Patent number: 11264481
    Abstract: Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: March 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Juntao Li
  • Patent number: 11180852
    Abstract: The present invention is in the field of processes for the generation of thin inorganic films on substrates, in particular atomic layer deposition processes. The present invention relates to a process for the generation of inorganic films comprising depositing the compound of general formula (I) onto a solid substrate (I), wherein M is Mn, Ni or Co, X is a ligand which coordinates M, n is 0, 1, 2, 3, or 4, R1 is an alkyl group, an alkenyl group, an aryl group, a halogen, or a silyl group, R2 is an alkyl group, an alkenyl group, an aryl group, or a silyl group, p and q are 1 or 2, wherein p+q=3, and m is 1, 2, or 3.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 23, 2021
    Assignee: BASF SE
    Inventors: Torben Adermann, Falko Abels, Carolin Limburg, Hagen Wilmer, Jan Gerkens, Sven Schneider
  • Patent number: 11177274
    Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang
  • Patent number: 11174551
    Abstract: Methods for forming a nucleation layer on a substrate. In some embodiments, the processing method comprises sequential exposure to a first reactive gas comprising a metal precursor and a second reactive gas comprising a halogenated silane to form a nucleation layer on the surface of the substrate.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: November 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kelvin Chan, Yihong Chen
  • Patent number: 11069785
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11018225
    Abstract: A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Renee T. Mo, Christopher Scerbo, Hongwen Yan, Jeng-Bang Yau
  • Patent number: 10998443
    Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsin Hu, Huan-Tsung Huang
  • Patent number: 10985105
    Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruley, Jack O. Chu, Kam-Leung Lee, Ahmet S. Ozcan, Paul M. Solomon, Jeng-bang Yau
  • Patent number: 10957778
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10907273
    Abstract: A method of growing epitaxial 3C-SiC on single-crystal silicon is disclosed. The method comprises providing a single-crystal silicon substrate in a cold-wall chemical vapour deposition reactor, heating the substrate to a temperature equal to or greater than 700° C. and equal to or less than 1200° C., introducing a gas mixture into the reactor while the substrate is at the temperature, the gas mixture comprising a silicon source precursor, a carbon source precursor and a carrier gas so as to deposit an epitaxial layer of 3C-SiC on the single-crystal silicon.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 2, 2021
    Inventors: Maksym Myronov, Gerard Colston, Stephen Rhead
  • Patent number: 10840349
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10797155
    Abstract: A semiconductor structure and a manufacturing method thereof are provided, wherein the semiconductor structure includes a substrate and gate structures. The gate structures are disposed on the substrate. Each of the gate structures includes a gate, a first spacer and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, the second spacers are separated from each other, and an upper portion of each of the second spacers has a recess. The semiconductor structure can be used to form a good metal silicide.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Zhenhai Zhang
  • Patent number: 10734410
    Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 4, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Rama Divakaruni
  • Patent number: 10658248
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming a mask layer on a top surface of the gate structure; forming pocket regions in the base substrate at both sides of the gate structure; after forming the pocket regions, forming a first protective portion covering a top surface of the mask layer and protruding from sidewall surfaces of the gate structure; and after forming the first protective portion, forming doped source/drain regions in the base substrate and portions of the pocket regions at both sides of the gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhao Xu Shen
  • Patent number: 10608096
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10553582
    Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonjae Kim, Cheol Kim, Yong-Hoon Son, Jin-Hyuk Yoo, Woojin Jung
  • Patent number: 10541139
    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10522641
    Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu
  • Patent number: 10505015
    Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10354996
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Patent number: 10134641
    Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: November 20, 2018
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Shuming Xu
  • Patent number: 9887290
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9837401
    Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Kun Huang, Shih-Che Lin, Hung-Chih Yu
  • Patent number: 9685434
    Abstract: Embodiments in accordance with the present invention include a method of fabricating a semiconductor device including forming a first dummy gate in an active area on a first portion of a semiconductor device, wherein the first dummy gate includes undoped amorphous silicon. A second dummy gate and a third dummy gate are formed on a second portion of the semiconductor device, wherein the second dummy gate and the third dummy gate include undoped amorphous silicon. A filling material is deposited on the semiconductor device, where the filling material is doped amorphous silicon, and a chemical-mechanical polishing process is performed on the filling material.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 9520402
    Abstract: Embodiments of the present disclosure are directed towards techniques to provide etch stops to the wordlines that form a staircase structure of a 3D memory array. In one embodiment, the apparatus may comprise a 3D memory array having wordlines disposed in a staircase structure. A wordline may include a silicide layer and a spacer disposed to abut the silicide layer around an end of the wordline. The silicide layer and the spacer may form an etch stop of the wordline for a wordline contact structure to electrically connect the wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop. The etch stop may be configured to prevent a physical or electrical contact of the wordline contact structure with an adjacent wordline of the staircase structure, in order to avoid undesired short circuits. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Gordon A. Haller, Jun Liu
  • Patent number: 8937012
    Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: January 20, 2015
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Hai Won Kim, Sang Ho Woo, Sung Kil Cho, Gil Sun Jang
  • Patent number: 8937349
    Abstract: A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 20, 2015
    Assignee: Sony Corporation
    Inventor: Koichi Amari
  • Patent number: 8889554
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 18, 2014
    Assignee: The Institue of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
  • Patent number: 8877597
    Abstract: When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Frank Feustel, Kai Frohberg
  • Patent number: 8841192
    Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tan-Chen Lee, Bor-Wen Chan
  • Patent number: 8834989
    Abstract: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuko Ikeda, Shinya Sasagawa, Hideomi Suzawa, Shunpei Yamazaki
  • Patent number: 8828858
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8765603
    Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Wei-Yang Lee, Xiong-Fei Yu, Kuang-Yuan Hsu
  • Patent number: 8754487
    Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuri Masuoka, Huan-Tsung Huang
  • Patent number: 8716790
    Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 6, 2014
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Jian Tan
  • Patent number: 8709897
    Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan
  • Patent number: 8691703
    Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 8, 2014
    Assignee: SK Hynix Inc.
    Inventors: Suk Ki Kim, Hyeon Soo Kim
  • Patent number: 8679894
    Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8658485
    Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Publication number: 20140042501
    Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Inventors: Jei-Ming Chen, Chih-Chien Liu, Yu-Shu Lin, Tzu-Chin Wu