Using Self-aligned Silicidation, I.e., Salicide (epo) Patents (Class 257/E21.438)
  • Patent number: 10734410
    Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 4, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Rama Divakaruni
  • Patent number: 10658248
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming a mask layer on a top surface of the gate structure; forming pocket regions in the base substrate at both sides of the gate structure; after forming the pocket regions, forming a first protective portion covering a top surface of the mask layer and protruding from sidewall surfaces of the gate structure; and after forming the first protective portion, forming doped source/drain regions in the base substrate and portions of the pocket regions at both sides of the gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhao Xu Shen
  • Patent number: 10608096
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10553582
    Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonjae Kim, Cheol Kim, Yong-Hoon Son, Jin-Hyuk Yoo, Woojin Jung
  • Patent number: 10541139
    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10522641
    Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu
  • Patent number: 10505015
    Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10354996
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Patent number: 10134641
    Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: November 20, 2018
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Shuming Xu
  • Patent number: 9887290
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9837401
    Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Kun Huang, Shih-Che Lin, Hung-Chih Yu
  • Patent number: 9685434
    Abstract: Embodiments in accordance with the present invention include a method of fabricating a semiconductor device including forming a first dummy gate in an active area on a first portion of a semiconductor device, wherein the first dummy gate includes undoped amorphous silicon. A second dummy gate and a third dummy gate are formed on a second portion of the semiconductor device, wherein the second dummy gate and the third dummy gate include undoped amorphous silicon. A filling material is deposited on the semiconductor device, where the filling material is doped amorphous silicon, and a chemical-mechanical polishing process is performed on the filling material.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 9520402
    Abstract: Embodiments of the present disclosure are directed towards techniques to provide etch stops to the wordlines that form a staircase structure of a 3D memory array. In one embodiment, the apparatus may comprise a 3D memory array having wordlines disposed in a staircase structure. A wordline may include a silicide layer and a spacer disposed to abut the silicide layer around an end of the wordline. The silicide layer and the spacer may form an etch stop of the wordline for a wordline contact structure to electrically connect the wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop. The etch stop may be configured to prevent a physical or electrical contact of the wordline contact structure with an adjacent wordline of the staircase structure, in order to avoid undesired short circuits. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Gordon A. Haller, Jun Liu
  • Patent number: 8937349
    Abstract: A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 20, 2015
    Assignee: Sony Corporation
    Inventor: Koichi Amari
  • Patent number: 8937012
    Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: January 20, 2015
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Hai Won Kim, Sang Ho Woo, Sung Kil Cho, Gil Sun Jang
  • Patent number: 8889554
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: November 18, 2014
    Assignee: The Institue of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang, Zhijiong Luo, Huilong Zhu
  • Patent number: 8877597
    Abstract: When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Frank Feustel, Kai Frohberg
  • Patent number: 8841192
    Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tan-Chen Lee, Bor-Wen Chan
  • Patent number: 8834989
    Abstract: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuko Ikeda, Shinya Sasagawa, Hideomi Suzawa, Shunpei Yamazaki
  • Patent number: 8828858
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
  • Patent number: 8815736
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Javorka, Stefan Flachowsky, Clemens Fitz
  • Patent number: 8765603
    Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Wei-Yang Lee, Xiong-Fei Yu, Kuang-Yuan Hsu
  • Patent number: 8754487
    Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuri Masuoka, Huan-Tsung Huang
  • Patent number: 8716790
    Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 6, 2014
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Jian Tan
  • Patent number: 8709897
    Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan
  • Patent number: 8691703
    Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 8, 2014
    Assignee: SK Hynix Inc.
    Inventors: Suk Ki Kim, Hyeon Soo Kim
  • Patent number: 8679894
    Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8658485
    Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Publication number: 20140042501
    Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Inventors: Jei-Ming Chen, Chih-Chien Liu, Yu-Shu Lin, Tzu-Chin Wu
  • Patent number: 8642435
    Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chang-Yin Chen, Zhe-Hao Zhang, Yi-Chen Huang
  • Patent number: 8642439
    Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
  • Patent number: 8642433
    Abstract: A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: February 4, 2014
    Assignee: Institute of Microelectronics, Academy of Sciences
    Inventors: Huicai Zhong, Jun Luo, Chao Zhao, Qingqing Liang
  • Publication number: 20130344673
    Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andreas Kurz, Peter Javorka, Sergej Mutas, Clemens Wündisch
  • Patent number: 8597975
    Abstract: A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 3, 2013
    Assignee: Altis Semiconductor
    Inventor: Faiz Dahmani
  • Publication number: 20130316506
    Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Shin-Chuan Huang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou
  • Patent number: 8574981
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: November 5, 2013
    Assignee: GlobalFoundries Inc.
    Inventors: Stefan Flachowsky, Thilo Scheiper, Peter Javorka, Jan Hoentschel
  • Patent number: 8574980
    Abstract: A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Craig H. Huffman
  • Patent number: 8563429
    Abstract: Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF3 and NH3, HF and NH3, and N2, H2, and NF3, dissociating the etchant source, forming an etchant of NH4F and NH4F.HF through the dissociation, producing solid by-products of (NH4)2SiF6 through the reaction between the etchant and an oxide at a low temperature, and annealing the by-products at a high temperature such that the by-products are sublimated into gas-phase SiF4, NH3, and HF.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Goo Hur, Kyu-Tae Na, Min Kim, Hyun-Young Kim, Je-Hyeon Park
  • Patent number: 8518765
    Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 27, 2013
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.
    Inventors: Anh Duong, Clemens Fitz, Olov Karlsson
  • Patent number: 8507378
    Abstract: A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: August 13, 2013
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: ChiKang Liu, ZhengYing Wei, GuoXu Zhao, YangFeng Li, GuoLiang Zhu, FangYu Yang
  • Publication number: 20130200442
    Abstract: A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Hsuan LIN, Chih-Hsun LIN, Ching-Hua CHU, Ling-Sung WANG
  • Publication number: 20130187171
    Abstract: A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicants: GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. GUILLORN, Christian LAVOIE, Ghavam G. SHAHIDI, Bin YANG, Zhen ZHANG
  • Patent number: 8492275
    Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 23, 2013
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Bin Yang
  • Patent number: 8470703
    Abstract: Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hak Lee, Yu-Gyun Shin, Sang-Woo Lee, Sun-Ghil Lee, Jin-Bum Kim, Joon-Gon Lee
  • Patent number: 8405131
    Abstract: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventor: Haining S. Yang
  • Publication number: 20130071981
    Abstract: A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 21, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chien-Chung HUANG, Nien-Ting HO
  • Publication number: 20130071977
    Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Stefan Flachowsky, Andy Wei
  • Publication number: 20130049128
    Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Stefan Flachowsky
  • Publication number: 20130026582
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Glyn Braithwaite