Abstract: A method for forming silicide in a semiconductor device includes simultaneously performing a cleaning process and an etching process to remove a silicide metal layer if an excessive delay in time lapses after forming the silicide metal layer. This may prevent the occurrence of liquid marks due to an oxidation reaction at an interface of the semiconductor substrate in contact with the silicide metal layer, thereby preventing silicide defects due to the excessive delay.

Abstract: A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.

Abstract: Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance.

Abstract: A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate.

Abstract: Embodiments relater to a semiconductor device and a method of fabricating the same. A source/drain area may be formed by using the spacer having the dual structure of the oxide layer and nitride layer. After etching a part of the oxide layer, the salicide layer may be formed on the gate electrode and the source/drain area, and the spacer may be removed. The contact area may be ensured, so a higher degree of integration may be achieved.

Abstract: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor pattern which is covered with a first insulating film over a first active region, forming a second semiconductor pattern over a second active region, forming a second insulating film over the first insulating film and the first and second semiconductor patterns, forming an opening whose depth reaches the first semiconductor pattern by etching the second insulating film and the first insulating film, forming sidewalls on side surfaces of the second semiconductor pattern by patterning the second insulating film, forming a metal film over the first and second semiconductor patterns respectively, and forming silicide layers by reacting the first and second semiconductor patterns with the metal film.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a refractory metal alloy layer over a silicon-containing conductive layer. The refractory metal alloy layer is constituted of a first refractory metal and a second refractory metal. Thereafter, a cap layer is formed on the refractory metal alloy layer. A thermal process is performed so that the refractory metal alloy layer reacts with silicon of the silicon-containing conductive layer to form a refractory metal alloy salicide layer. Afterwards, an etch process with an etch solution is performed to removes the cap layer and the refractory metal alloy layer which has not been reacted and to form a protection layer on the refractory metal alloy salicide layer.

Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Abstract: A self-aligned field-effect transistor (FET) is provided. The self-aligned FET includes a substrate, a dielectric layer, conductive electrodes, and a carbon nanotube. A patterned back-gated conductive electrode is disposed in the substrate. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer and function as a source/drain. The patterned source/drain conductive electrodes contain a metal silicide such as cobalt silicide serve as a catalyst for carbon nanotube synthesis. The carbon nanotube is disposed on the dielectric layer to be electrically connected with the source/drain conductive electrodes.

Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

Abstract: Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask.

Abstract: A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer and the metal layer are silicided due to a thermal budget applied thereto, thereby forming a metal silicide layer, and patterning the metal silicide layer based on the hard mask to form a gate.

Abstract: Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.

Abstract: A method of manufacturing a transistor in which gate resistance is lowered and short channel effects are controlled by forming a trench-type gate. The threshold voltage can also be more tightly controlled.

Abstract: In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a single-crystalline silicon substrate and on a polysilicon pattern, and partially etching the preliminary metal silicide pattern to form a first metal silicide pattern on the substrate and a second metal silicide pattern on the polysilicon pattern, the second metal silicide pattern having a line width the same as or smaller than that of the polysilicon pattern. The method may include the transistor having no metal silicide residue on the spacer. Accordingly, an operation failure due to the residue may be prevented or reduced.

Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.

Abstract: In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Abstract: A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a first temperature. The polysilicon layer is then annealed with the substrate to raise the polysilicon layer to a second temperature higher than the first temperature. A photoimageable layer is then deposited over the polysilicon layer, after which an alignment signal including light from the alignment feature is received through the annealed polysilicon layer. Using the alignment signal passing through the annealed polysilicon layer from the alignment feature, an exposure system is aligned with the substrate with improved results.

Abstract: A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (30, 32, 34) using a first metal (e.g., cobalt). After forming sidewall spacers (40, 42), a second metal (e.g., nickel) is used to form second silicide regions in the polysilicon, source and drain regions (60, 62, 64) to reduce encroachment by the second silicide in the source/drain (62, 64) and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide (30).

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.

Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.

Abstract: MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a silicon substrate having an impurity-doped region disposed at a surface of the silicon substrate. A first layer is sputter-deposited onto the impurity-doped region using a first sputtering target comprising nickel and a first concentration of platinum. A second layer is sputter-deposited onto the first layer using a second sputtering target comprising nickel and a second concentration of platinum, wherein the second concentration of platinum is less than the first.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract: According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a silicon-containing layer over a semiconductor substrate, forming a metal layer over the semiconductor substrate and the silicon-containing layer, forming a silicide-containing layer over the semiconductor substrate and the silicon-containing layer by heat treatment of the semiconductor substrate and the silicon-containing layer, and applying flash annealing to the silicide-containing layer.

Abstract: A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.

Abstract: A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern over the substrate; forming a first salicide on an exposed portion of the substrate and a second salicide on an entire upper surface of the second conductive pattern; depositing a third insulating layer over the substrate, and etching selectively the third insulating layer to forming first and second contact holes exposing the first and second salicides. The method provides processing margin and prevents excessive etching of a conductive layer under the salicide, even if misalignment of an overlying contact hole happens.

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.

Abstract: Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C.

Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method can include forming a first barrier pattern to cover a first region of a semiconductor substrate while exposing second and third regions of the semiconductor substrate, forming a first oxide layer pattern on the second and third regions, forming a second barrier pattern to cover the third region while exposing the first and second regions, forming a second oxide layer pattern on the first and second regions, forming a third oxide layer pattern on the second region by removing the second and first oxide layer patterns formed on the first and third regions, forming a silicide metal layer on the first, second, and third regions, and selectively forming silicide on the first and third regions by performing an annealing process with respect to the silicide metal layer.

Abstract: A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched back to expose a surface of the substrate. The silicon nitride layer is removed to form a gate sidewall spacer. Impurity ions are implanted into the substrate through the exposed surface of the substrate.

Abstract: A method of fabricating a semiconductor device comprises the step of forming a nickel monosilicide layer selectively over a silicon region defined by an insulation film by a self-aligned process. The self-aligned process comprises the steps of forming a metallic nickel film on a silicon substrate on which the insulation film and the silicon region are formed, such that the metallic nickel film covers the insulation film and the silicon region, forming a first nickel silicide layer primarily of a Ni2Si phase on a surface of the silicon region of the metallic nickel film by applying an annealing process to the silicon substrate, removing the metallic nickel film, after the step of forming the first nickel silicide layer, by a selective wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of a NiSi phase by a thermal annealing process conducted in a silane gas.

Abstract: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a metallic nickel film on a silicon substrate such that the metallic nickel film covers an insulation film on the silicon substrate and a silicon surface of the silicon substrate, annealing the silicon substrate in a silane gas ambient at a temperature not exceeding 220° C. to form a first nickel silicide layer having a composition primarily of Ni2Si on the silicon surface and a surface of the metallic nickel film, removing the metallic nickel film after the step of forming the nickel silicide layer by a wet etching process, and converting the first nickel silicide layer to a second nickel silicide layer primarily of nickel monosilicide (NiSi) by applying a thermal annealing process.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip.

Abstract: The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.