Using Dummy Gate Wherein At Least Part Of Final Gate Is Self-aligned To Dummy Gate (epo) Patents (Class 257/E21.444)
  • Patent number: 10861851
    Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
  • Patent number: 10795257
    Abstract: A method for forming a functionalised guide pattern for the self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern made of a first material having a first chemical affinity for the block copolymer, the guide pattern having a cavity with a bottom and side walls; grafting a functionalisation layer made of a second polymeric material having a second chemical affinity for the block copolymer, the functionalisation layer having a first portion grafted onto the bottom of the cavity and a second portion grafted onto the side walls of the cavity; selectively etching the second portion of the functionalisation layer relative to the first portion of the functionalisation layer, the etching including a step of exposure to an ion beam following a direction that intersects the second portion of the functionalisation layer, such that the ion beam does not reach the first portion of the functionalisation layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 6, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier
  • Patent number: 10714616
    Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 10707331
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
  • Patent number: 10665696
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 26, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, National Taiwan University
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • Patent number: 10651093
    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Y. Liu, Michael L. Hattendorf
  • Patent number: 10559661
    Abstract: The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 11, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10510894
    Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun Chang, Ming-Ching Chang, Shu-Yuan Ku
  • Patent number: 10468257
    Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
  • Patent number: 10340349
    Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao
  • Patent number: 10304742
    Abstract: A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10276718
    Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Wang, Yung Feng Chang, Tung-Heng Hsieh
  • Patent number: 10170323
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
  • Patent number: 10043814
    Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Yamashita
  • Patent number: 10032634
    Abstract: A method includes forming a gate stack over a semiconductor substrate; forming an interlayer dielectric layer surrounding the gate stack; and at least partially removing the gate stack, thereby forming an opening. The method further includes forming a multi-function wetting/blocking layer in the opening, a work function layer over the multi-function blocking/wetting layer, and a conductive layer over the work function layer. The work function layer, the multi-function wetting/blocking layer, and the conductive layer fill the opening. The multi-function wetting/blocking layer includes aluminum, carbon, nitride, and one of: titanium and tantalum.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Patent number: 10014223
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9947592
    Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie-Cheng Deng, Yi-Jen Chen, Horng-Huei Tseng
  • Patent number: 9748141
    Abstract: Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; forming a dielectric layer on the substrate to substantially cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate; etching the dielectric layer back to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 29, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 9728642
    Abstract: A method for fabricating a semiconductor device comprises patterning a strained fin from a strained layer of semiconductor material arranged on a substrate, depositing a first layer of semiconductor material on the fin and exposed portions of the substrate, patterning and etching to remove a portion of the first layer of semiconductor material and a portion of the fin to expose a portion of the substrate, depositing a second layer of semiconductor material on exposed portions of the substrate and the first layer of semiconductor material, and patterning and etching to remove a portion of the second layer of semiconductor material layer and the first layer of semiconductor material to define a dummy gate stack, the dummy gate stack is operative to substantially maintain the strain in the strained fin.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Gauri Karve, Fee Li Lie, Junli Wang
  • Patent number: 9659779
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9620377
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Lab Research Corporation
    Inventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyung Joo Shin
  • Patent number: 9613963
    Abstract: A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second device region. A p-type fin field effect transistor is formed in the first device region. The p-type fin field effect transistor has a first fin structure constituted of a first semiconductor material. An n-type fin field effect transistor is formed in the second device region. The n-type fin field effect transistor has a second fin structure constituted of a second semiconductor material that is different than the first semiconductor material. To fabricate the semiconductor device, a substrate having an active layer present on a dielectric layer is provided. The active layer is etched to provide a first region having the first fin structure and a second region having a mandrel structure. The second fin structure is formed on a sidewall of the mandrel structure.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9530670
    Abstract: The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 27, 2016
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Hoon Han, Byoung-Moon Yoon, Young-Taek Hong, Keon-Young Kim, Jun-Youl Yang, Young-Ok Kim, Tae-Heon Kim, Sun-Joong Song, Jung-Hun Lim, Jae-Wan Park, Jin-Uk Lee
  • Patent number: 9530891
    Abstract: A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Ota, Toshinori Numata, Masumi Saitoh, Chika Tanaka
  • Patent number: 9508815
    Abstract: A semiconductor device is provided including a substrate and a plurality of gate stacks. The gate stack includes a dielectric layer disposed on the substrate, a first capping layer disposed on the dielectric layer, a second capping layer disposed on the first capping layer, and a gate electrode layer covering the second capping layer. The first capping layer having a roughened surface may enhance the formation of the second capping layer. The second capping layer has a bottom portion and a sidewall portion, and the thickness of the bottom portion is formed to be greater than the thickness of the sidewall portion, so that the dielectric property of the second capping layer may be significantly improved. Further, a method for manufacturing the semiconductor device also provides herein.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-An Li, Cheng-Chun Tsai, Ting-Hsien Chen, Mu-Kai Tung, Ben-Zu Wang, Po-Jen Shih, Hung-Hsin Liang
  • Patent number: 9397101
    Abstract: A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: HariKrishna Chintarlapalli Reddy, Jay Madhukar Shah, Ananth Haliyur Gopalakrishna
  • Patent number: 9390975
    Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Helmut Horst Tews
  • Patent number: 9356108
    Abstract: Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huei-Ru Liou, Chien-Chih Chou, Kong-Beng Thei, Gwo-Yuh Shiau
  • Patent number: 9343529
    Abstract: A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk substrate. The material stack and a portion of the bulk substrate are then patterned by etching to provide an intermediate fin structure including a base semiconductor portion and alternating portions of the silicon etch stop material and the germanium nanowire template material. After recessing each germanium nanowire template material and optionally the base semiconductor portion, and etching each silicon etch stop material to define a new fin structure, a spacer is formed on sidewall surfaces of the remaining portions of the new fin structure. The alternating layers of germanium nanowire template material are then suspended above a notched surface portion of the bulk substrate and thereafter a functional gate structure is formed.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9331204
    Abstract: A high-voltage circuit is described that comprises a high-voltage finFET can have a semiconductor fin with an insulating cap on the fin. A gate dielectric is disposed on the first and second sides of the fin. A gate overlies the gate dielectric and a channel region in the fin on the first and second sides, and over the cap. Source/drain terminals are disposed on opposing sides of the gate in the fin, and can include lightly doped regions that extend away from the edge of the gate to more highly doped contacts. The dimensions of the structures can be configured so that the transistor has a breakdown voltage of 30 V or higher.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 3, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 9331146
    Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita
  • Patent number: 9263290
    Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 9041058
    Abstract: A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 26, 2015
    Assignee: SONY CORPORATION
    Inventor: Yasushi Tateshita
  • Patent number: 9035319
    Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Jung-hee Lee, Ki-sik Im, Dong-seok Kim, Hee-sung Kang, Dong-hyeok Son
  • Patent number: 8987099
    Abstract: The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Su-Hao Liu, Tsan-Chun Wang
  • Patent number: 8969163
    Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael V. Aquilino, Byeong Yeol Kim, Ying Li, Carl John Radens
  • Patent number: 8921825
    Abstract: A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8916460
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • Patent number: 8901665
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
  • Patent number: 8901675
    Abstract: A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Weihai Bu, Wenbo Wang, Shaofeng Yu, Hanming Wu
  • Patent number: 8883623
    Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: November 11, 2014
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Xiuyu Cai, Pranatharthiharan Balasubramanian, Shom Ponoth
  • Patent number: 8883582
    Abstract: During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Uwe Griebenow, Katrin Reiche, Heike Berthold
  • Patent number: 8884375
    Abstract: A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Nakai, Masato Suga, Jusuke Ogura
  • Patent number: 8859378
    Abstract: Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: October 14, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qingqing Liang, Huicai Zhong, Huilong Zhu
  • Patent number: 8853084
    Abstract: A method provides an intermediate semiconductor device structure and includes providing a wafer having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non-planar wafer surface topography due at least to a presence of the first dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8841726
    Abstract: An intermediate wafer includes a substrate having a surface and a first dummy gate plug disposed upon a structure, e.g., a FIN, supported by the substrate surface; a second dummy gate plug disposed upon the substrate surface; and a first layer in which the first dummy gate plug and the second dummy gate plug are embedded. The first layer exhibits a non-planar surface topography characterized by a depression due at least to a presence of the first dummy gate plug. The structure further includes a second layer that fills the depression to the surface of the first layer, and a third layer that overlies the first layer and the second layer. The third layer is formed of a hard mask material and has a substantially planar surface topography over the first and second dummy gate plugs and over the depression that is filled with the material of the second layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8835237
    Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sanjay Mehta
  • Patent number: 8828813
    Abstract: The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Meng-Chun Chang
  • Patent number: 8822290
    Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Meng-Ku Chen, Huicheng Chang
  • Patent number: 8802518
    Abstract: A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 12, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Chao Zhao, Kai Han, Dapeng Chen