With Pn Homojunction Gate (epo) Patents (Class 257/E21.446)
  • Patent number: 10218394
    Abstract: A method and system of providing an active differential resistor. The active differential resistor includes a diode having a first node and a second node. There is a capacitor coupled in series between the first node of the diode and an input of the active differential resistor. There is a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: February 26, 2019
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventor: Michael Thomas Engelhardt
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 8623722
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20130248944
    Abstract: According to one embodiment, a junction type field effect transistor includes a first conductive type semiconductor substrate, a first conductive type drift layer, a second conductive type gate region, a first conductive type channel layer, a first conductive type source region, a source electrode, a drain electrode, a second conductive type gate contact layer, and a gate electrode. The drift layer is provided on a first main surface of the semiconductor substrate. The gate region is provided on a surface of the drift layer. The channel layer is provided on the drift layer and the gate region. The source region is provided on a surface of the channel layer to face the gate region, and has an impurity concentration higher than the channel layer. The source electrode is provided on the channel layer with Schottky contact and on the source region with ohmic contact.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kohei MORIZUKA
  • Patent number: 8329568
    Abstract: In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: December 11, 2012
    Assignee: Xilinx, Inc.
    Inventors: Jae-Gyung Ahn, Myongseob Kim, Ping-Chin Yeh, Zhiyuan Wu, John Cooksey
  • Publication number: 20120256238
    Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).
    Type: Application
    Filed: April 6, 2011
    Publication date: October 11, 2012
    Inventors: Tak H. Ning, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8247286
    Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ryul Chang
  • Patent number: 8035138
    Abstract: A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor substrate; a first conductivity type epitaxial layer formed on the second conductivity type epitaxial layer; a second conductivity type source region which penetrates the first conductivity type epitaxial layer in a layer thickness direction thereof and is connected to the second conductivity type epitaxial layer; a second conductivity type drain region which is spaced from the source region, penetrates the first conductivity type epitaxial layer in the layer thickness direction, and is connected to the second conductivity type epitaxial layer; a source electrode connected to the source region; a drain electrode connected to the drain region; and a gate electrode electrically connected to the first conductivity type epitaxial layer between the source region and the drain region.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Shouji Higashida
  • Publication number: 20110227093
    Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiro HIKITA, Hidetoshi ISHIDA, Tetsuzo UEDA
  • Publication number: 20110212583
    Abstract: A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
    Type: Application
    Filed: April 1, 2011
    Publication date: September 1, 2011
    Inventor: Philip G. Neudeck
  • Publication number: 20110198669
    Abstract: The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 18, 2011
    Applicant: Furukawa Electric Co., Ltd.
    Inventors: Shusuke Kaya, Nariaki Ikeda, Jiang Li
  • Patent number: 7943971
    Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: May 17, 2011
    Assignee: SuVolta, Inc.
    Inventors: Ashok K. Kapoor, Damodar R. Thummalapally
  • Publication number: 20110101424
    Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuinness, Bernard Patrick Stenson, William Allan Lane
  • Patent number: 7915107
    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 29, 2011
    Assignee: SuVolta, Inc.
    Inventor: Ashok K. Kapoor
  • Publication number: 20100207173
    Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 19, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frederick G. Anderson, David S. Collins, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
  • Publication number: 20100171155
    Abstract: Silicon-on-insulator JFET having a body bias and a fully depleted body and fabrication methods therefore are disclosed. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time), and have poor leakage performance at high temperatures. The techniques herein introduced include a fully-depleted body SOI-JFET, with a non-zero bias applied to its body. In one example, the body region of the JFET can be fully depleted by tuning the thickness of the silicon containing layer of the SOI substrate. Additionally, the deep depletion can be induced by applying a non-zero bias to the body region, at a range of operating temperatures. Full body depletion and/or the application of body bias offers the benefits of suppressed leakage current at higher operating temperatures (e.g., between or above 25-115 C) and improved AC performance (e.g., faster switching time).
    Type: Application
    Filed: January 8, 2009
    Publication date: July 8, 2010
    Inventor: Samar Kanti Saha
  • Patent number: 7745274
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Publication number: 20100133593
    Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Applicant: DSM Solutions, Inc.
    Inventor: Srinivasa R. Banna
  • Patent number: 7709311
    Abstract: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: May 4, 2010
    Assignee: SuVolta, Inc.
    Inventors: Samar K. Saha, Ashok K. Kapoor
  • Patent number: 7687834
    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 30, 2010
    Assignee: SuVolta, Inc.
    Inventor: Ashok K. Kapoor
  • Publication number: 20100025739
    Abstract: A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
  • Publication number: 20090302355
    Abstract: A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Inventors: John J. Pekarik, Richard A. Phelps, Robert M. Rassel, Yun Shi
  • Publication number: 20090302356
    Abstract: A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and a silicon layer. An epi-silicon layer is formed in the buried insulation layer of the peripheral region and connects a peripheral portion of a channel area of the silicon layer to the silicon substrate. A gate is formed on the silicon layer and junction areas are formed in the silicon layer on both sides of the gate.
    Type: Application
    Filed: December 12, 2008
    Publication date: December 10, 2009
    Inventor: Ki Bong NAM
  • Publication number: 20090258464
    Abstract: Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Renata Camillo-Castillo, Robert J. Gauthier, JR., Richard A. Phelps, Andreas D. Stricker
  • Patent number: 7569873
    Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: August 4, 2009
    Assignee: DSM Solutions, Inc.
    Inventor: Ashok K. Kapoor
  • Patent number: 7569437
    Abstract: By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: August 4, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Wirbeleit, Andy Wei, Roman Boschke
  • Publication number: 20090181503
    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device.
    Type: Application
    Filed: March 16, 2009
    Publication date: July 16, 2009
    Inventors: Anup Bhalla, Francois Hebert, Daniel S. Ng
  • Publication number: 20090101941
    Abstract: A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Applicant: International Business Machines Corporation
    Inventors: John Ellis-Monaghan, Richard A. Phelps, Robert M. Rassel, Steven H. Voldman, Michael J. Zierak
  • Publication number: 20090017585
    Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 15, 2009
    Applicant: DSM Solutions, Inc.
    Inventor: Ashok Kumar Kapoor
  • Publication number: 20080299716
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Application
    Filed: July 21, 2008
    Publication date: December 4, 2008
    Inventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
  • Publication number: 20080272393
    Abstract: A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from the source region and the gate region abutting the channel region. The channel region includes a channel layer having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer and applies a stress to the channel region along a boundary between the substrate layer and the channel layer.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 6, 2008
    Applicant: DSM Solutions, Inc.
    Inventor: Ashok K. Kapoor
  • Publication number: 20080272407
    Abstract: A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 6, 2008
    Applicant: DSM Solutions, Inc.
    Inventor: Ashok K. Kapoor
  • Publication number: 20080272406
    Abstract: Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 6, 2008
    Applicant: DSM SOLUTIONS, INC.
    Inventor: Srinivasa R. Banna
  • Publication number: 20080272394
    Abstract: Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
    Type: Application
    Filed: October 10, 2007
    Publication date: November 6, 2008
    Inventors: Ashok Kumar Kapoor, Madhukar B. Vora, Weimin Zhang, Sachin R. Sonkusale, Yujie Liu
  • Publication number: 20080258182
    Abstract: A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
    Type: Application
    Filed: October 13, 2005
    Publication date: October 23, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Prabhat Agarwal, Jan W. Slotboom, Wibo Van Noort
  • Publication number: 20080093635
    Abstract: A shallow channel region is selectively formed by ion implantation and diffusion. Since the channel region forms pn junctions with a p type semiconductor layer having a relatively low impurity concentration, a reduction of a junction capacitance leads to improvement in high-frequency characteristics. Moreover, since a gate region can also be shallowly formed by ion implantation, noise can be reduced by reduction in an internal resistance. Furthermore, a breakdown voltage and electrostatic breakdown characteristics can be improved by allowing the source and drain regions to penetrate the channel region.
    Type: Application
    Filed: October 23, 2007
    Publication date: April 24, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Shunsuke KOBAYASHI
  • Publication number: 20080076212
    Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Basanth JAGANNATHAN, John Pekarik, Christopher Schnabel
  • Publication number: 20080054312
    Abstract: A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor substrate; a first conductivity type epitaxial layer formed on the second conductivity type epitaxial layer; a second conductivity type source region which penetrates the first conductivity type epitaxial layer in a layer thickness direction thereof and is connected to the second conductivity type epitaxial layer; a second conductivity type drain region which is spaced from the source region, penetrates the first conductivity type epitaxial layer in the layer thickness direction, and is connected to the second conductivity type epitaxial layer; a source electrode connected to the source region; a drain electrode connected to the drain region; and a gate electrode electrically connected to the first conductivity type epitaxial layer between the source region and the drain region.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 6, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Shouji Higashida
  • Publication number: 20070281408
    Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.
    Type: Application
    Filed: August 16, 2007
    Publication date: December 6, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Gregory Howard, Leland Swanson
  • Publication number: 20070281407
    Abstract: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate stricture (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.
    Type: Application
    Filed: August 16, 2007
    Publication date: December 6, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Gregory Howard, Leland Swanson