Vertical Transistor, E.g., Tecnetrons (epo) Patents (Class 257/E21.447)
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Patent number: 9954529Abstract: Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.Type: GrantFiled: March 21, 2017Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, Albert M. Chu, Edward J. Nowak
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Patent number: 9666696Abstract: A method of manufacturing a vertical junction field effect transistor (JFET) includes forming a drain in a semiconductor substrate, forming a compound semiconductor epitaxial layer on the semiconductor substrate, and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source.Type: GrantFiled: November 6, 2015Date of Patent: May 30, 2017Assignee: Infineon Technologes Austria AGInventors: Romain Esteve, Cédric Ouvrard
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Patent number: 8835893Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.Type: GrantFiled: May 9, 2012Date of Patent: September 16, 2014Assignee: Micron Technology, Inc.Inventors: Jun Liu, Mike Violette
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Patent number: 8829574Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.Type: GrantFiled: December 22, 2011Date of Patent: September 9, 2014Assignee: Avogy, Inc.Inventors: Donald R. Disney, Isik C. Kizilyalli, Hui Nie, Linda Romano, Richard J. Brown, Madhan Raj
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Patent number: 8659057Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: GrantFiled: May 20, 2011Date of Patent: February 25, 2014Assignee: Power Integrations, Inc.Inventors: Andrew Ritenour, David C. Sheridan
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Publication number: 20130292686Abstract: A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Applicant: AVOGY, INC.Inventors: Isik C. Kizilyalli, Linda Romano, David P. Bour
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Patent number: 8524552Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: GrantFiled: January 31, 2012Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20130161705Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: EPOWERSOFT, INC.Inventors: Don Disney, Isik C. Kizilyalli, Hui Ne, Linda Romano, Richard J. Brown, Madhan Raj
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Publication number: 20130164893Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: EPOWERSOFT, INC.Inventors: Linda Romano, David P. Bour, Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, Thomas R. Prunty
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Patent number: 8466017Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.Type: GrantFiled: December 8, 2010Date of Patent: June 18, 2013Assignee: Power Integrations, Inc.Inventors: David C. Sheridan, Andrew Ritenour
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Publication number: 20130087835Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Applicant: EPOWERSOFT, INC.Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
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Publication number: 20130032811Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: EPOWERSOFT, INC.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Publication number: 20130032812Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: EPOWERSOFT, INC.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Patent number: 8354678Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.Type: GrantFiled: July 11, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Benjamin A. Fox, Nathaniel J. Gibbs, Andrew B. Maki, David M. Onsongo, Trevor J. Timpane
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Publication number: 20130009215Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: Infineon Technologies AGInventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
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Publication number: 20130011979Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: SS SC IP, LLCInventors: Andrew RITENOUR, David C. SHERIDAN
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Publication number: 20120261675Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.Type: ApplicationFiled: March 30, 2012Publication date: October 18, 2012Applicant: SS SC IP, LLCInventors: Janna CASADY, Jeffrey CASADY, Kiran CHATTY, David SHERIDAN, Andrew RITENOUR
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Publication number: 20120193641Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Patent number: 8193521Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.Type: GrantFiled: May 19, 2010Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventors: Jun Liu, Mike Violette
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Publication number: 20120074469Abstract: A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.Type: ApplicationFiled: September 23, 2010Publication date: March 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
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Patent number: 8119471Abstract: A method for manufacturing a semiconductor device including a vertical double-diffusedmetal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type.Type: GrantFiled: August 8, 2011Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Patent number: 8105868Abstract: The invention pertains to a method for making a solar cell module comprising solar cells connected in series, comprising the steps of: a) making in a system composed of a substrate-overlaid by a first electrode layer, itself overlaid by an active layer, a first, interruption, groove providing an interrupt in the front electrode and the active layer and a second, interconnection, groove through the active layer, the first and second grooves being positioned close to each other; b) inserting an insulating compound into the interruption groove; c) applying a lift-off compound onto the active layer at a position adjacent to the interconnection groove on the other side of the interconnection groove than the insulation groove; d) applying the second electrode; e) removing the lift-off compound and the overlaying second electrode at that position to obtain a groove in the second electrode.Type: GrantFiled: December 21, 2007Date of Patent: January 31, 2012Assignee: Helianthos B.V.Inventors: Jan Winkeler, Gerrit C. Dubbeldam, Peter E. Sportel
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Publication number: 20110291107Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: ApplicationFiled: May 20, 2011Publication date: December 1, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: Andrew Ritenour, David C. Sheridan
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Publication number: 20110156054Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Applicant: DENSO CORPORATIONInventors: Yuuichi TAKEUCHI, Rajesh Kumar Malhan, Naohiro Sugiyama
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Publication number: 20110133212Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.Type: ApplicationFiled: December 8, 2010Publication date: June 9, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. SHERIDAN, Andrew RITENOUR
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Publication number: 20110127587Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.Type: ApplicationFiled: July 9, 2010Publication date: June 2, 2011Applicant: Hynix Semiconductor Inc.Inventor: Hee Jung YANG
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Publication number: 20110020991Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: ApplicationFiled: October 1, 2010Publication date: January 27, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. SHERIDAN, Andrew P. RITENOUR
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Patent number: 7859026Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.Type: GrantFiled: March 16, 2006Date of Patent: December 28, 2010Assignee: Spansion LLCInventor: William A. Ligon
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Patent number: 7799623Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first or second semiconductor layer. The region contacts the insulation layer, and the region is disposed between a source and a drain of the LDMOS transistor. The device has high withstand voltage in a direction perpendicular to the substrate.Type: GrantFiled: December 15, 2009Date of Patent: September 21, 2010Assignee: DENSO CORPORATIONInventor: Akira Yamada
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Patent number: 7772103Abstract: In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence.Type: GrantFiled: June 26, 2008Date of Patent: August 10, 2010Assignee: Samsung Electronics Co. LtdInventors: Ho-Jun Yi, Yong-Il Kim, Bong-Soo Kim, Dae-Young Jang, Woo-Jeong Cho
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Patent number: 7763506Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.Type: GrantFiled: September 10, 2007Date of Patent: July 27, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Heinz Mitlehner, Rudolf Elpelt, Peter Friedrichs, Larissa Wehrhahn-Kilian
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Patent number: 7745273Abstract: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type.Type: GrantFiled: July 30, 2007Date of Patent: June 29, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Michael Rueb, Rudolf Elpelt
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Publication number: 20100148186Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: ApplicationFiled: November 5, 2009Publication date: June 17, 2010Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. Sheridan, Andrew P. Ritenour
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Patent number: 7586130Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.Type: GrantFiled: February 1, 2006Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Takahiro Kawashima, Tohru Saitoh, Takeshi Takagi
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Publication number: 20090184396Abstract: Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at least one of aluminum oxide and titanium oxide. The variable resistance layer is a metal oxide layer.Type: ApplicationFiled: October 20, 2008Publication date: July 23, 2009Inventors: Ki-hwan Kim, Young-soo Park, Myung-jae Lee, Xianyu Wenxu, Seung-eon Ahn, Chang-bum Lee
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Publication number: 20090108303Abstract: A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization structure, which is arranged opposite the first metallization structure, is electrically coupled to the charge compensation zones via a Schottky contact and to drift zones via an ohmic contact.Type: ApplicationFiled: October 30, 2008Publication date: April 30, 2009Applicant: Infineon Technologies Austria AGInventor: Frank Pfirsch
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Publication number: 20090078971Abstract: A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Michael Treu, Roland Rupp, Rudolf Elpelt
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Publication number: 20090068803Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Heinz Mitlehner, Rudolf Elpelt, Peter Friedrichs, Larissa Wehrhahn-Kilian
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Patent number: 7476590Abstract: A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body.Type: GrantFiled: September 22, 2005Date of Patent: January 13, 2009Assignee: Nissan Motor Co., Ltd.Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Yoshio Shimoida, Hideaki Tanaka
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Publication number: 20080124853Abstract: Semiconductor devices and methods of making the devices are described. The devices can be implemented in SiC and can include epitaxially grown n-type drift and p-type trenched gate regions, and an n-type epitaxially regrown channel region on top of the trenched p-gate regions. A source region can be epitaxially regrown on top of the channel region or selectively implanted into the channel region. Ohmic contacts to the source, gate and drain regions can then be formed. The devices can include edge termination structures such as guard rings, junction termination extensions (JTE), or other suitable p-n blocking structures. The devices can be fabricated with different threshold voltages, and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used as discrete power transistors and in digital, analog, and monolithic microwave integrated circuits.Type: ApplicationFiled: November 6, 2007Publication date: May 29, 2008Applicants: SEMISOUTH LABORATORIES, INC., MISSISSIPPI STATE UNIVERSITYInventors: Lin Cheng, Michael S. Mazzola
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Patent number: 7364997Abstract: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.Type: GrantFiled: July 7, 2005Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Werner Juengling