Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.

Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. An impurity such as hydrogen or moisture (e.g., a hydrogen atom or a compound containing a hydrogen atom such as H2O) is eliminated from an oxide semiconductor layer with use of a halogen element typified by fluorine or chlorine, so that the impurity concentration in the oxide semiconductor layer is reduced. A gate insulating layer and/or an insulating layer provided in contact with the oxide semiconductor layer can be formed to contain a halogen element. In addition, a halogen element may be attached to the oxide semiconductor layer through plasma treatment under an atmosphere of a gas containing a halogen element.

Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a copper species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.

Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method forms a bulk copper indium disulfide material from a multi-layered structure comprising a copper species, an indium species, and a sulfur species overlying the first electrode layer. The bulk copper indium disulfide material comprises one or more portions of a copper poor copper indium disulfide material, a copper poor surface regions, and one or more portions of a sulfur deficient copper indium disulfide material characterized by at least a CuInS2-x species, where 0<x<2. The copper poor surface and one or more portions of the copper poor copper indium disulfide material are subjected to a sodium species derived from a sodium sulfide material to convert the copper poor surface from an n-type characteristic to a p-type characteristic.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A fin-semiconductor region (13) is formed on a substrate (11). A first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in an upper portion and side portions of the fin-semiconductor region (13), and oxygen or nitrogen is further introduced as a second impurity in the upper portion and side portions of the fin-semiconductor region (13).

Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Abstract: A method for forming a thin film photovoltaic device is provided. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A chalcopyrite material is formed overlying the first electrode layer. In a specific embodiment, the chalcopyrite material comprises a copper poor copper indium disulfide region. The copper poor copper indium disulfide region having an atomic ratio of Cu:In of about 0.95 and less. The method includes compensating the copper poor copper indium disulfide region using a sodium species to cause the chalcopyrite material to change from an n-type characteristic to a p-type characteristic. The method includes forming a window layer overlying the chalcopyrite material and forming a second electrode layer overlying the window layer.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subject at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material includes one or more portions of copper indium disulfide material characterized by a copper-to-indium atomic ratio of less than about 0.95:1 and a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material comprises one or more portions of copper indium disulfide material and a copper poor surface region characterized by a copper-to-indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A laser medium comprises a solid-state host material and dopant species provided within the solid-state host material. A first portion of the dopant species has a first valence state, and a second portion of the dopant species has a second valence state. In an embodiment, a concentration of the first portion of the dopant species decreases radially with increasing distance from a center of the medium, and a concentration of the second portion of the dopant species increases radially with increasing distance from the center of the medium. The laser medium further comprises impurities within the solid-state host material, the impurities converting the first portion of the dopant species having the first valence state into the second portion of dopant species having the second valence state.

Abstract: A method of making a doped metal oxide comprises heating a first doped metal oxide with a laser, to form a crystallized doped metal oxide. The crystallized doped metal oxide has a different crystal structure than the first doped metal oxide.

Abstract: Phosphorous-comprising dopants, methods for forming phosphorous-doped regions in a semiconductor material, and methods for fabricating phosphorous-comprising dopants are provided. In one embodiment, a phosphorous-comprising dopant comprises a phosphorous source comprising a phosphorous-comprising salt, a phosphorous-comprising acid, phosphorous-comprising anions, or a combination thereof, an alkaline material, cations from an alkaline material, or a combination thereof, and a liquid medium.

Abstract: An electrically actuated device comprises an active region (16) disposed between a first electrode (12) and a second electrode (14), a fixed dopant (24) distributed within the active region, and at least one type of mobile dopant situated near an interface between the active region and the second electrode.

Abstract: A method for forming a thin film photovoltaic device is provided. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A chalcopyrite material is formed overlying the first electrode layer. In a specific embodiment, the chalcopyrite material comprises a copper poor copper indium disulfide region. The copper poor copper indium disulfide region having an atomic ratio of Cu:In of about 0.95 and less. The method includes compensating the copper poor copper indium disulfide region using a sodium species to cause the chalcopyrite material to change from an n-type characteristic to a p-type characteristic. The method includes forming a window layer overlying the chalcopyrite material and forming a second electrode layer overlying the window layer.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subject at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material includes one or more portions of copper indium disulfide material characterized by a copper-to-indium atomic ratio of less than about 0.95:1 and a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material comprises one or more portions of copper indium disulfide material and a copper poor surface region characterized by a copper-to-indium atomic ratio of less than about 0.95:1.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.

Abstract: A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.

Abstract: A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewalls of the silicon mandrels in a process that leaves sidewall portions of the silicon mandrels doped with impurities and that leaves central portions of at least some of the silicon mandrels undoped. The method removes the cap layer to leave the silicon mandrels standing on the primary layer and performs a selective material removal process to remove the central portions of the silicon mandrels and to leave the sidewall portions of the silicon mandrels standing on the primary layer. The method patterns at least the primary layer using the sidewall portions of the silicon mandrels as a patterning mask and removes the sidewall portions of the silicon mandrels to leave at least the primary layer patterned.

Abstract: This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed.

Abstract: A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.

Abstract: A method for diffusing two dissimilar dopant materials onto a semiconductor cell wafer in a single thermal processing step. The method includes placing a first dopant source on a semiconductor cell wafer, placing said cell wafer into a thermal processing chamber comprising one or more cell wafer slots, subjecting said cell wafer to a thermal profile; and annealing said cell wafer in the presence of a second dopant source.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Abstract: A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region.

Abstract: A subject of the present invention is to realize an impurity doping not to bring about a rise of a substrate temperature. Another subject of the present invention is to measure optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized. An impurity doping method, includes a step of doping an impurity into a surface of a solid state base body, a step of measuring an optical characteristic of an area into which the impurity is doped, a step of selecting annealing conditions based on a measurement result to meet the optical characteristic of the area into which the impurity is doped, and a step of annealing the area into which the impurity is doped, based on the selected annealing conditions.

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract: The invention relates to a method for the precision processing of substrates, in particular for the microstructuring of thin layers, local dopant introduction and also local application of a metal nucleation layer in which a liquid-assisted laser, i.e. laser irradiation of a substrate which is covered in the regions to be processed by a suitable reactive liquid, is implemented.

Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract: The present invention generally relates to nanotechnology and sub-microelectronic circuitry, as well as associated methods and devices, for example, nanoscale wire devices and methods for use in determining nucleic acids or other analytes suspected to be present in a sample (for example, their presence and/or dynamical information), e.g., at the single molecule level. For example, a nanoscale wire device can be used in some cases to detect single base mismatches within a nucleic acid (e.g., by determining association and/or dissociation rates). In one aspect, dynamical information such as a binding constant, an association rate, and/or a dissociation rate, can be determined between a nucleic acid or other analyte, and a binding partner immobilized relative to a nanoscale wire. In some cases, the nanoscale wire includes a first portion comprising a metal-semiconductor compound, and a second portion that does not include a metal-semiconductor compound.

Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Abstract: Method for producing doped regions on the rear face of a photovoltaic cell. A doping paste with a first type of conductivity is deposited on a rear face of a semiconductor-based substrate according to a pattern consistent with the desired distribution of regions doped with the first type of conductivity. Then, an oxide layer is deposited at least on the portions of the rear face of the substrate not covered with the doping paste. Finally, an annealing of the substrate diffuses the doping agents in the substrate and forms doped regions under the doping paste.

Abstract: A method of manufacturing silicon nano wires including forming microgrooves on a surface of a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate and forming a second doping layer doped with a second dopant between the first doping layer and a surface of the silicon substrate, forming a metal layer on the silicon substrate, forming catalysts by heating the metal layer within the microgrooves of the silicon substrate and growing the nano wires between the catalysts and the silicon substrate using a thermal process.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine, and crystallizing the melt to form a single crystal which contains fluorine within the range of 1·1010 to 1·1016 atoms/cm3, at a growth rate at which agglomerated intrinsic point defects having a critical diameter or larger would arise if fluorine were not present or present in too small an amount, and separating semiconductor wafers from the single crystal.

Abstract: A method for forming an electronic device provides a carrier formed from a composite material comprising a plastic binder and an embedded material. A substrate material is attached to the carrier. The substrate is processed to form the electronic device thereon. The substrate is then detached from the carrier to yield the resultant electronic device.

Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.

Abstract: The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film.