Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

Abstract: Semiconductor devices comprising a flip-chip having passive circuits such as spiral inductors on the back side are disclosed. Provision is made for connection with the spiral inductors using vias and/or bondwires. Further aspects of the invention provide for methods of making such devices.

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element.

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract: The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.

Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

Abstract: An oxide transistor includes: a channel layer formed of an oxide semiconductor; a source electrode contacting a first end portion of the channel layer; a drain electrode contacting a second end portion of the channel layer; a gate corresponding to the channel layer; and a gate insulating layer disposed between the channel layer and the gate. The oxide semiconductor includes hafnium-indium-zinc-oxide (HfInZnO). An electrical conductivity of a back channel region of the channel layer is lower than an electrical conductivity of a front channel region of the channel layer.

Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

Abstract: The instant disclosure relates to a metal oxide thin film transistor having a threshold voltage modification layer. The thin film transistor includes a gate electrode, a dielectric layer formed on the gate electrode, an active layer formed on the dielectric layer, a source electrode and a drain electrode disposed separately on the active layer, and a threshold voltage modulation layer formed on the active layer in direct contact with the back channel of the transistor. The threshold voltage modulation layer and the active layer have different work functions so that the threshold voltage modulation layer modulates the threshold voltage of devices and improve the performance of the transistor.

Abstract: An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen into an oxide semiconductor layer, a transistor in which an oxynitride semiconductor having desired carrier density and on characteristics is used for a channel can be manufactured. Further, with the use of the oxynitride semiconductor, even when a low resistance layer or the like is not provided between an oxynitride semiconductor layer and a source electrode and between the oxynitride semiconductor layer and a drain electrode, favorable contact characteristics can be exhibited.

Abstract: A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed.

Abstract: An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.

Abstract: A high bandwidth semiconductor printed circuit board assembly (PCBA) providing a layer of dielectric substrate containing plated vias with an upper and lower surface plated with etched copper, mated with a second layer of etched copper plated dielectric containing plated vias that is placed on the top surface of the first layer. A third layer of etched copper plated dielectric containing plated vias may be placed on the bottom layer of etched copper foil. A base layer of etched copper plated thick dielectric containing plated vias is laminated simultaneously with the preceding layers to provide the high bandwidth digital and RF section of the assembly.

Abstract: A thin-film transistor (TFT) includes a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode and an etch stopper. The gate electrode is formed on a substrate. The oxide semiconductor pattern is disposed in an area overlapping with the gate electrode. The source electrode is partially disposed on the oxide semiconductor pattern. The drain electrode is spaced apart from the source electrode, faces the source electrode, and is partially disposed on the oxide semiconductor pattern. The etch stopper has first and second end portions. The first end portion is disposed between the oxide semiconductor pattern and the source electrode, and the second end portion is disposed between the oxide semiconductor pattern and the drain electrode. A sum of first and second overlapping length is between about 30% and about 99% of a total length of the etch stopper.

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

Abstract: A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.

Abstract: The invention relates to a method for producing vertical electrical connections in semiconductor wafers, the method including the following steps: application of a protective resist to the wafer front side; patterning of the protective resist such that the contacts to be connected to the wafer rear side become free; laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side; cleaning of the wafer; application of a plating base to the wafer rear side and into the laser-drilled passage holes; application of gold by electrodeposition onto the metallized wafer rear side and the passage holes; resist stripping of the protective resist; and application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.

Abstract: A transparent electrode on at least one surface of a transparent substrate may include graphene doped with a p-dopant. The transparent electrode may be efficiently applied to a variety of display devices or solar cells.

Abstract: A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include a gate electrode formed on a substrate; an active layer made of an oxide semiconductor and insulated from the gate electrode by a gate insulating layer; source and drain electrodes coupled to the active layer; and an interfacial stability layer formed on one or both surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristic as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

Abstract: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer on the wiring line after step (b); and (d) forming a protective layer on a second surface opposite to the first surface of the semiconductor substrate after step (c).

Abstract: A switchable electronic device comprises a hole blocking layer and a layer comprising a conductive material between first and second electrodes, wherein the conductivity of the device may be irreversibly switched upon application of a current having a current density of less than or equal to 100 A cm?2 to a conductivity at least 100 times lower than the conductivity of the device before switching. The conductive material is a doped organic material such as doped optionally substituted poly(ethylene dioxythiophene).

Abstract: A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu—OSP can be formed over the substrate.

Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.

Abstract: A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.

Abstract: A backplane having a circuit array having at least one region comprising a substrate having a conductive plane under a dielectric surface, a first conductive layer on said dielectric surface, a selectively disposed insulator disposed over said first conductive layer, and a second conductive layer disposed on said insulator, wherein said first conductive layer is electrically insulated from said second conductive layer, said first conductive layer being formed electrographically, and said second conductive layer being formed by a process comprising selective deposition of liquid droplets, which are then solidified. The second conductive layer may be formed electrographically or by a raster deposition process. The backplane preferably forms an active matrix for a flat panel display using organic semiconductor active elements.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.

Abstract: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.

Abstract: A staggered thin film transistor and a method of forming the staggered thin film transistor are provided. The thin film transistor includes an annealed layer stack including an oxide containing layer, a copper alloy layer deposited on the conductive oxide layer, a copper containing oxide layer, and a copper containing layer.

Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed over the substrate; and a gate electrode formed over the compound semiconductor layer with a gate insulating film arranged therebetween. The gate insulating film includes a first layer having reverse spontaneous polarization, the direction of which is opposite to spontaneous polarization of the compound semiconductor layer.

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate.

Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

Abstract: A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copper layer that is coplanar with a dielectric layer. In one embodiment, the ILD is silicon nitride with 100 to 600 Angstrom thickness. After a via opening is formed in a photoresist layer above the copper layer, a first RIE process including BARC main etch and BARC over etch steps is performed. Then a second RIE step transfers the opening through the ILD to uncover the copper layer. Photoresist and BARC are stripped with oxygen plasma and a low DC bias. Wet cleaning may involve a first ST250 treatment, ultrasonic water treatment, and then a third ST250 treatment. A bottom electrode layer may be deposited in the via opening.

Abstract: A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.

Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

Abstract: A thin film transistor, a method of manufacturing the thin film transistor, and a flat panel display device including the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; a gate insulating film formed on the gate electrode; an activation layer formed on the gate insulating film; a passivation layer including a compound semiconductor oxide, formed on the activation layer; and source and drain electrodes that contact the activation layer.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: Transistors, methods of manufacturing the transistors, and electronic devices including the transistors. The transistor may include an oxide channel layer having a multi-layer structure. The channel layer may include a first layer and a second layer that are sequentially arranged from a gate insulation layer. The first layer may be a conductor, and the second layer may be a semiconductor having a lower electrical conductivity than that of the first layer. The first layer may become a depletion region according to a gate voltage condition.

Abstract: A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

Abstract: A thin film transistor, which has a first passivation layer and a second passivation layer to maintain high reliability while preventing hydrogen from being induced to a semiconductor layer, and a method for fabricating the thin film transistor are provided. The method includes providing a substrate including an insulation substrate, forming a gate electrode on the substrate, forming a gate insulation layer on the substrate and the gate electrode, forming a semiconductor layer on the gate insulation layer, forming source/drain electrodes on the semiconductor layer to expose a portion of a top portion of the semiconductor layer, forming a first passivation layer to cover exposed top portions of the gate insulation layer, the semiconductor layer and the source/drain electrodes, and forming a second passivation layer on the first passivation layer, wherein the forming of the second passivation layer comprises performing deposition at a higher temperature than the forming of the first passivation layer.

Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

Abstract: In at least some embodiments, a thin-film transistor (TFT) includes a gate electrode and a gate dielectric covering the gate dielectric. The TFT also includes a source electrode and a drain electrode adjacent the gate dielectric. The TFT also includes a bi-layer channel between the source electrode and the drain electrode, the bi-layer channel having a zinc indium oxide (ZIO) layer positioned adjacent the gate dielectric and a zinc tin oxide (ZTO) layer that covers the ZIO layer.

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract: A process for applying blocking contacts on an n-type CdZnTe specimen includes cleaning the CdZnTe specimen; etching the CdZnTe specimen; chemically surface treating the CdZnTe specimen; and depositing blocking metal on at least one of a cathode surface and an anode surface of the CdZnTe specimen.

Abstract: It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 50 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 50 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of ruthenium, rhodium, and iridium.

Abstract: WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies.

Abstract: A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads.